The ARM processor has a total of 37 registers. These include:
- 31 general-purpose registers, including the program counter (PC). These registers are all 32-bit registers.
- 6 status registers, these registers are all 32-bit registers, but only 12 of them are currently used.
The ARM processor has 7 different processor modes, and there is a corresponding set of registers in each processing mode. At any time, the visible registers include 15 general-purpose registers (R0~R14), one or two status registers and the program counter. Among all registers, some are the same physical register shared by each mode; some are independent physical registers owned by each mode. The following table lists the register conditions visible in various processor modes.
Registers in Various Processor Modes
| user mode | system mode | Privileged mode | abort mode | Undefined command mode | External Interrupt Mode | fast interrupt mode |
| R0 | R0 | R0 | R0 | R0 | R0 | R0 |
| R1 | R1 | R1 | R1 | R1 | R1 | R1 |
| R2 | R2 | R2 | R2 | R2 | R2 | R2 |
| R3 | R3 | R3 | R3 | R3 | R3 | R3 |
| R4 | R4 | R4 | R4 | R4 | R4 | R4 |
| R5 | R5 | R5 | R5 | R5 | R5 | R5 |
| R6 | R6 | R6 | R6 | R6 | R6 | R6 |
| R7 | R7 | R7 | R7 | R7 | R7 | R7 |
| R8 | R8 | R8 | R8 | R8 | R8 | R8_FIQ |
| R9 | R9 | R9 | R9 | R9 | R9 | R9_FIQ |
| R10 | R10 | R10 | R10 | R10 | R10 | R10_FIQ |
| R11 | R11 | R11 | R11 | R11 | R11 | R11_FIQ |
| R12 | R12 | R12 | R12 | R12 | R12 | R12_FIQ |
| R13 | R13 | R13_SVC | R13_ABT | R13_AND | R13_IRQ | R13_FIQ |
| R14 | R14 | R14_SVC | R14_ABT | R14_AND | R14_IRQ | R14_FIQ |
| PC | PC | PC | PC | PC | PC | PC |
| CPSR | CPSR | CPSR | CPSR | CPSR | CPSR | CPSR |
| SPSR_SVC | SPSR_ABT | SPSR_AND | SPSR_IRQ | SPSR_FIQ |
General register introduction:
General purpose registers can be divided into the following three categories:
- Registers not backed up, including R0~R7;
- Backup registers, including R8~R14;
- The program counter, or R15.
Registers not backed up:
Unbacked registers include R0~R7. For each unbacked register, it refers to the same physical register in all processor modes. When the abnormal interrupt causes the processor mode to switch, since different processor modes use the same physical register, the data in the register may be damaged. Unbacked registers are not used by the system for special purposes, and any application that uses general-purpose registers can use unbacked registers.
Backup registers:
For backup registers R8~R12, each register corresponds to two different physical registers. For example, when using the register in fast interrupt mode, register R8 and register R9 are respectively recorded as R8_FIQ, R9_FIQ; when using the register in user mode, register R8 and R9 are respectively recorded as R8_USR, R9_USR, etc. In both cases, different physical registers are used. The system does not use these registers for special purposes, but when the interrupt processing is very simple, and only the R8~R14 registers are used, the FIQ handler does not need to execute the instructions to save and restore the interrupt scene, so that the interrupt processing process can be very fast. .
For the backup registers R13 and R14, each register corresponds to 6 different physical registers, one of which is shared by the user mode and the system mode, and the other 5 correspond to the other 5 processor modes. The following notations are used to distinguish each physical register.
R13_<mode>
Where <mode> can be one of the following: usr, svc, abt, und, irq, and fiq.
Register R13 is often used as a stack pointer (sp) in ARM. In the ARM instruction set, this is just a habitual usage, and there is no instruction forcing the use of R13 as the stack pointer. Users can also use other registers as the stack pointer; while in the Thumb instruction set, some instructions force the use of R13 as the stack pointer. stack pointer.
Each anomalous mode has its own physical R13. The application initializes this R13 to point to the stack address dedicated to this exception mode. When entering the exception mode, the register to be used can be saved in the stack pointed to by R13; when the exception handler is exited, the register value saved in the stack pointed by R13 will be popped. This keeps the exception handler from destroying the execution context of the program it interrupted.
Register R14 is also known as the connection register (LR), which has the following two special functions in the ARM system:
The return address of the current subroutine is stored in each processor mode's own physical R14. When a subroutine is called by a BL jump instruction, R14 is set to the return address of the subroutine. In the subroutine, when the value of R14 is copied to the program counter PC, the subroutine returns. The return operation of this subroutine can be realized in the following two ways.
Execute any of the following instructions:
MOV PC, LR
BX LR
Use the following instruction at subroutine entry to save the PC to the stack:
STMFD SP!, {<registers>, LR}
Correspondingly, the following instruction can realize the return of the subroutine:
LDMFD SP!, {<register>, PC}
When an exception interrupt occurs, the exception mode-specific physical register R14 is set to the address to which the exception mode will return. For some exception modes, the value of R14 may have a constant offset from the address to be returned. The specific return method is basically the same as the return method of the above subroutine.
The R14 register can also be used as a general-purpose register.
Program counter R15 (PC):
The program counter R15 is again referred to as PC. Although it can be used as a general general-purpose register, some instructions have some special restrictions when using R15. When these restrictions are violated, the results of execution of this instruction will be unpredictable.
Because ARM adopts the pipeline mechanism, when the value of PC is read correctly, the value is the address of the current instruction plus 8 bytes. That is to say, for the ARM instruction set, the PC points to the address of the next two instructions of the current instruction. Since ARM instructions are byte aligned, bits 0 and 1 of the PC value are always 0.
It should be noted that when the instruction STR/STM is used to save R15, the current instruction address value plus 8 bytes may be saved, or the current instruction address plus 12 bytes may be saved. Which way it is depends on how the chip is designed. In any case, in the same chip, either use the current instruction address plus 8, or use the current instruction address plus 12 bytes, some instructions cannot use the current instruction address plus 8, and other instructions use the current instruction address plus 12. Therefore, for users, try to avoid using the STM/STR instruction to save the value of R15. When this usage is unavoidable, some code can first determine which method is used by the chip used. Assuming that R0 points to an available memory word, the following code returns the address offset used by the chip in the memory word pointed to by R0.
SUB R1, PC ,#4 @R1 stores the address of the following STR instruction
STR PC, [R0] @PC=STR address plus offset is stored in R0
LDR R0, [R0]
SUB R0, R0, R1 @offset=PC-STR address
In the above discussion, it is for the value returned by the instruction. This value is not the value that appeared on the data bus during an instruction fetch. The value that appears on the data bus during an instruction fetch depends on the specific implementation of the chip.
When an address value is successfully written to R15, the program will jump to this address for execution. Since the ARM instruction is word-aligned, the address value written to R15 should satisfy bits[1:0]=0b00. As for the specific requirements, each version of ARM is different.
For the Thumb instruction set, instructions are nibble aligned. The processor will ignore bit[0], that is, the address value written to R15 is first ANDed with 0xFFFFFFFE, and then written to R15.
There are also some instructions that have some special requirements for the usage of R15. For example, the instruction BX uses bit[0] to determine whether it is an ARM instruction or a Thumb instruction.
This asymmetric operation of reading the PC value and writing the PC value requires special attention. This will be covered in later chapters. For example, the instruction "MOV PC, PC" will jump the program to the second instruction below the current instruction for execution. Because in the instruction, the value read from the second PC register is the address value of the current instruction plus 8, so for the ARM instruction, the address of the second instruction below the current instruction is written to the PC register. Similar instructions are "ADD PC, PC, #0".
Program Status Register:
The CPSR (Current Program Status Register) can be accessed in any processor mode. It contains condition flags, interrupt disable bits, current processor mode flags, and other control and status bits. Each processor mode has a dedicated physical status register called SPSR (Backup Program Status Register). When a specific abnormal interrupt occurs, this register is used to store the contents of the current program status register. When the aborted program exits, the CPSR can be restored with the value stored in the SPSR.
Since user mode and system mode are not aborted modes, they do not have SPSRs. When accessing the SPSR in user mode or system mode, there will be unpredictable results.
The format of the CPSR is shown below. The format of SPSR is the same as that of CPSR.
| 31 | 30 | 29 | 28 | 27 | 26 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| N | WITH | C | V | Q | DNM | I | F | T | M4 | M3 | M2 | M1 | M0 |
Condition flags:
N (Negative), Z (Zero), C (Carry) and V (oVerflow) are collectively referred to as condition flags. Most ARM instructions can be selectively executed based on these conditional flags in the CPSR. The specific meaning of each condition flag bit is shown in the following table.
Condition flag bits in CPSR
| flag bit | meaning |
| N | This bit is set to bit[31] of the operation result of the current instruction; when the signed integer operation is represented by two's complement, N=1 means that the result of the operation is a negative number, and N=0 means that the result is a positive number or zero. |
| WITH | Z=1 means that the result of the operation is zero; Z=0 means that the result of the operation is not zero. For the CMP instruction, Z=1 means that the two numbers being compared are equal in size |
| C | The setting method of C is discussed in the following four cases: In the addition instruction, when the result produces a carry, then C=1, indicating that the unsigned number operation has overflowed; in other cases, it is 0; In the subtraction instruction, when a borrow occurs in the operation, C=0, indicating that the unsigned number operation has an underflow, and it is 0 in other cases; For other non-add/subtract instructions, the value of the C bit is generally unaffected. |
| V | For addition/subtraction instructions, when the operand and the result of the operation are signed numbers represented by two's complement, V=1 means the sign bit overflows. |
The following instructions affect the condition flag bits in the CPSR:
- Compare instructions, such as CMP, CMN, TEQ, and TST, etc.;
- When the destination register of some arithmetic operation instructions and logic instructions is not R15, these instructions will affect the condition flag bit in the CPSR;
- MSR instructions can write new values to CPSR/SPSR;
- When the MSC instruction uses R15 as the target register, the value of the condition flag bit generated by the coprocessor can be transferred to the ARM processor;
- Some variants of the LDM instruction can copy the value of the SPSR to the CPSR. This operation is used to return from the abnormal interrupt program;
- Some variants of arithmetic and logic instructions with "bit setting" can also copy the value of SPSR into CPSR, which is mainly used for returning from abnormal interrupt routine.
Q flag bit: In the E series processors of ARMv5, bit[27] of CPSR is called the Q flag bit, which is mainly used to indicate whether an overflow has occurred in the enhanced DSP instruction. Bit[27] in the same SPSR is also called the Q flag bit, which is used to save and restore the Q flag bit in the CPSR when an abnormal interrupt occurs.
Control bits in CPSR:
CPSR的低8位I、F、T及M[4：0]统称为控制位。当异常中断发生时，这些位发生变化。在特权级的处理器模式下，软件可以修改这些控制位。
(1)中断禁止位：
当I=1时禁止IRQ中断；
当F=1时禁止FIQ中断；
(2)T控制位：
T控制位用于控制指令执行的状态，即说明指令是ARM指令，还是Thumb指令。对于不同版本的ARM处理器，T控制位的含义不同。
对于ARMv4以及更高的版本的T系列的ARM处理器，T控制位的含义如下：
T=0表示执行的ARM指令；
T=1表示执行的Thumb指令；
(3)M控制位：
控制位M[4:0]控制处理器模式，具体含义如下表所示：
| M[4：0] | 处理器模式 | 可访问的寄存器 |
| 0b10000 | User | PC,R0~R14,CPSR |
| 0b10001 | FIQ | PC,R0~R7,R8_fiq~R14_fiq,CPSR,SPSR_fiq |
| 0b10010 | IRQ | PC,R0~R7,R8_irq~R14_irq,CPSR,SPSR_irq |
| 0b10011 | Supervisor | PC,R0~R7,R8_svc~R14_svc,CPSR,SPSR_svc |
| 0b10111 | Abort | PC,R0~R7,R8_abt~R14_abt,CPSR,SPSR_abt |
| 0b11011 | Undefined | PC,R0~R7,R8_und~R14_und,CPSR,SPSR_und |
| 0b11111 | System | PC,R0~R14,CPSR |
CPSR中其他位：CPSR中的其它位用于将来ARM版本的扩展，应用软件不要操作这些位，以免与ARM将来版本的扩展冲突。