Introduction to the ARM instruction set

Introduction to ARM instructions

The ARM instruction set is an instruction designed for the ARM architecture. In the first stage of BootLoader booting and the first stage of the kernel, there will be a file written in assembly language. There is also a piece of assembly code used to initialize the development board environment in the bare board that does not run the operating system. So whether it is developing a board with an operating system or bare board development, assembly language is very necessary to learn a little, at least to understand some commonly used assembly instructions. To design a system with superior performance, the working principle of ARM must be mastered.

ARM instruction set can be divided into the following six

• Jump instruction
• Data processing instructions
• Program status register transfer instruction
• Load / Store instruction
• Coprocessor instruction
• Abnormal interrupt instruction

The typical arm instruction syntax is: <opcode> {<cond>} {s} <Rd>, <Rn>, <shifter_operand>

• <opcode>: instruction mnemonic, such as ADD, SUB and other instructions.
• {<cond>}: indicates conditional execution ¹ .
• {S}: Determine whether the operation of the instruction affects the value of CPSR.
• <Rd>: target register.
• <Rn>: indicates the register containing the first operand.
• <shifter_operand>: indicates the second operand.

ARM instruction addressing mode

ARM instruction addressing refers to finding the address of an operand. Addressing methods can be divided into:

• The addressing mode of the operand of the data processing instruction.
• Load / Store instruction addressing mode.

Operand addressing of data processing instructions

The operands of these instructions have three formats: immediate number ² , register mode (the operand is the value of the register), and register shift mode (the operand is the corresponding shift in the value in the register). Register shift mode ³ : ASR (arithmetic right shift), LSL (logical left shift), LSR (logical right shift), ROR (cyclic right shift), RRX (cyclic right shift with extension), shifted bits The number can be expressed as an immediate value or as a register. So there are 11 kinds of addressing modes for data processing instructions.

• #< immediate >
• < Rm >
• < Rm >,LSL，#<shirt_imm>
• < Rm >,LSL，#< Rs>
• < Rm >,LSR，#< shirt_imm>
• < Rm >,LSR，#< Rs>
• < Rm >,ASR，#< shirt_imm>
• < Rm >,ASR，#< Rs>
• < Rm >,ROR，#< shirt_imm>
• < Rm >,ROR，#< Rs>
• < Rm >,RRX

load / store operand addressing

Word and unsigned byte load / store instruction addressing

The addressing mode of the load / store instruction consists of two parts. One part is a base address register, and the other part is an address offset. There are three formats for address offset: immediate, register, and register shift . There are three kinds of address calculation methods in the same addressing mode: ordinary offset, pre-update method, and post-update method.

• The common offset method is to directly add and subtract the value in the base address register and the offset, which is expressed as [<Rn>, address offset].
• Prior update method: update before use, expressed as [<Rn>, address offset] ! , use! Indicates the update method in advance.
• Post-event update method: use the value in the base address register and then update, expressed as [<Rn>] , address offset , followed by [], followed by the address offset indicates post-event update.
  So 9 addressing modes can be combined:
• [ < Rn >,#+/-< offset_12>]
• [ < Rn>,+/-< Rm>]
• [< Rn>,+/-< Rm>,< shift>#< shift_imm>]
• [ < Rn >,#+/-< offset_12>]!
• [ < Rn>,+/-< Rm>]!
• [< Rn>,+/-< Rm>,< shift>#< shift_imm>]!
• [ < Rn >],#+/-< offset_12>
• [ < Rn>],+/-< Rm>
• [<Rn>] , + /-<Rm>, <shift> # <shift_imm> The
  pre-update method and the post-update method refer to the process of processing the value and offset value in the base address register first, and then use. The base address register is updated after using the value in the base address register. Similar to ++ val and val ++ in C language.

Bulk load / store addressing mode

When you need to load or store a large amount of data, you can use the bulk load / Store instruction operation. A batch instruction can transfer data between a set of registers and a continuous memory unit. Transfer up to 16 memory unit data at a time. The correspondence between the register and the memory unit in the instruction is that the register with the lower number corresponds to the lower address unit in the memory.
The format is: LDM | STM {<cond>} <addressing_mode> <Rn> {!}, <Registers> {^} <addressing_code> indicates how the address changes, there are the following four types:

• IA (increment After): Incremental afterwards. The first register corresponds to the memory unit as the unit memory pointed to by the base register <Rn>. Then add 4 bytes in sequence
• IB (Increment Before): increasing in advance. The first register corresponds to the memory unit where the memory unit is the base address register <Rn> + 4. Then add 4 bytes in sequence
• DA (Decrement After): Decrement afterwards. The first register corresponds to the memory unit is the unit memory indicated by the base address register <Rn>-4 * (total number of registers -1). Then add 4 bytes in sequence
• DB (Decrement Before): Decrease in advance. The first register corresponds to the memory unit whose memory unit is the base address register <Rn> -4 * (total number of registers). Then add 4 bytes in sequence

For normal data transmission, the load instruction and store instruction can use the same addressing mode. But for the operation of the data stack, the order in which data is written to and read from memory is different, so the addressing methods used are different. The stack addressing modes are: FD, ED, FA, EA ⁴ .

Miscellaneous load / store instruction addressing mode

Miscellaneous instructions include load / store instructions with half-word operands, signed bytes, and double bytes. The syntax format is:
LDR | STR {<cond>} H | SH | SB | D <Rd>, <addressing_mode>

• H: Half-word interview.
• S: Character data.
• B: Byte data access.
• W: Double word access.
  There are only 6 kinds of addressing methods: addressing methods include ordinary offset, pre-update method, and post-update method . The format of the offset is: immediate value, register . So combine 6 addressing modes:
• [< Rn >,#+/-< offset_8>]
• [< Rn >,+/-< Rm >]
• [< Rn >,#+/-< offset_8>]!
• [< Rn >,+/-< Rm >]!
• [< Rn >],#+/-< offset_8>
• [< Rn >],+/-< Rm >

ARM instruction set

Jump instruction

There are two ways to achieve program jumps in ARM: use jump instructions and write the target address value directly to the PC . The difference between the two is that the PC register is directly operated, and any jump (long jump) can be achieved in the 4GB address space. ARM's jump instruction can jump forward or backward from the current instruction to the 32MB address space. The instructions are B, BL, BLX, BX L. Save the PC value in the LR register, X jump with state switching (you can switch to the thumb instruction set, the instruction type at the target address is determined by the bit [0] of the target address ).

Data processing instructions

Data processing instructions can be divided into three categories: data transfer instructions, arithmetic logic operation instructions, and comparison instructions. For the calculation method of operands, please refer to the addressing mode part of the data processing instruction mentioned above. The arithmetic logic instruction will store the result in the target register, and update the price adjustment flag bit in the CPSR. The comparison instruction does not save the operation result, but only updates the corresponding condition flag in the CPSR.

• Data transmission instructions are: MOV MVN
  MOV | MVN {<cond>} {s} <Rd>, <shifter-operand>
  MOV (MVN) instruction is to transfer the data (inverse code) represented by <shifter_operand> to the target register < Rd> Medium.
  note: MOVS PC, LR instruction can realize return from some abnormal interruption. The PC is the target register and the S bit is set. When the instruction is executed, the value of the SPSR corresponding to the current processor mode is copied to the CPSR.

• The comparison instructions are: CMP CMN TST TEQ
  <opcode> {<cond>} <Rn>, <shifter_operand> The
  CMP instruction is to update the corresponding condition flag in the CPSR according to the value of <Rn>-<shifet_operand> Bit.
  The CMN instruction is to update the value of <Rn> + <shifet_operand> and the corresponding condition flag bit in CPSR according to the operation result.
  The TST instruction is to perform bitwise AND operation on the value in <Rn> and the value of <shifet_operand>, and update the corresponding condition flag bit in CPSR according to the operation result.
  The TEQ instruction is to perform a bitwise XOR operation between the value in <Rn> and the value of <shifet_operand>, and update the corresponding condition flag bit in the CPSR according to the operation result.

• The arithmetic logic instructions are ADD SUB RSB ADC SBC RSC AND BIC EOR ORR
  <opcode> {<cond>} {s} <Rd>, <Rn>, <shifter_operand>

ADD adds the operand to the value in register <Rn> and saves the result to the destination register.
The ADC has a bit addition instruction, and adds the value of the C condition flag bit in CPSR on the basis of ADD.
eg: Add 64-bit operands. A 64-bit source operand is placed in R0 and R1, the lower 33 bits are placed in R0, and a 64-bit source operand is also placed in R2 and R3. The lower 32 bits
ADDS R4, R0, R2
ADC R5, R1, R3 ==> R5R4 is the calculated result
SUB, SUC subtraction instruction and bit subtraction instruction. SUC subtracts the inverse of the C condition flag in CPSR on the basis of SUB. The combination of these two instructions can also perform 64-bit subtraction.
SUBS R4, R0, R2
SUC R5, R1, R3
RSB, RSC reverse subtraction instruction and bitwise reverse subtraction instruction. <Rd> = <shifter_operand>-<Rn>

Multiplication instruction: (not much used for this)

• MUL: 32-bit multiplication instruction.
• MLA: 32-bit multiply instruction with addend.
• SMULL: 64-bit signed number multiplication instruction.
• SMLAL: 64-bit signed multiplication instruction with addend.
• UMULL: 64-bit unsigned multiplication instruction.
• UMLAL: 64-bit unsigned multiplication instruction with addition.

CLZ {<cond>} <Rd>, <Rm>. The instruction is used to count the number of 0s at the highest end of the operand in the register.
The division operation in the ARM instruction set is implemented by a coprocessor, so there is no division arithmetic instruction.

AND, ORR, EOR, and BIC are bitwise logical AND, OR, XOR, and clear operations, respectively.

Program status register transfer instruction

There are two instructions in ARM for transferring data between the status register and the general register. The program cannot directly change the program state to the thumb state by directly modifying the T control bit in the CPSR. The program state must be switched through instructions such as BX. Normally, the modification of the program status register is realized by "read-> modify-> write".

• Transfer instruction from MSR general register to status register. That is written.
• Transfer instruction from MRS status register to general register. Read.

Load / Store instruction

The load instruction is used to read data from the memory into the register, and the store instruction is used to save the data in the register to the memory.

For large amounts of moved data, ARM also provides bulk Load / Store memory access instructions. The batch load instruction can read data from consecutive memory cells at once and transfer them to registers. The batch store instruction is to write the multiple register values ​​in the register list into the memory by the opposite sex.

LDM | STM {<cond>} <addressing_mode> Rn {!}, <Registers> {^}
** in the command! ** After the instruction is executed, the memory address of the operand will be written into the base address register <Rn>, that is, the base address will be updated.
^ Means that the SPSR value in the current processor mode is copied into the CPSR when the instruction is executed. When the PC is not included in the register, the register used in the instruction instruction is a register in the user mode.

There is a special instruction in the data transfer instruction. The operation requirement for the semaphore is an atomic operation (cannot be interrupted, that is, there is only one instruction). The SWP instruction is used for semaphore operations when it finishes reading and modifying registers.
swp {<cond>} <Rd>, <Rm>, [<Rn>] The result of the execution is to read the contents of Rn into Rd and write the contents of Rm register into Rn.

Coprocessor instruction

ARM coprocessor instructions include the following three categories:

• It is used for the data processing operation of the ARM processor to initialize the ARM coprocessor. CDP
• Used for data transfer operations between registers of the ARM processor and registers of the ARM coprocessor. MCR, MRC
• Used to transfer data between registers and memory units of the ARM coprocessor. LDC, STC

CDP coprocessor operation instructions. The CDP instruction allows the ARM processor to notify the ARM coprocessor to perform a specific operation, which is completed by the coprocessor.

The LDC instruction reads data from consecutive memory units into the coprocessor's registers. The STC instruction writes the data in the coprocessor's registers to a series of memory cells.
Format:
LDC {<cond>} {L} <coproc>, <CRd>, <addressing_mode>
LDC2 {L} <coproc>, <CRd>, <addressing_mode>

STC {< cond >} {L} < coproc > , < CRd > ,< addressing_mode >
STC2 { L } < coproc >, < CRd >, < addressing_mode >

The MCR instruction transfers the data in the register of the ARM processor to the register of the coprocessor, while the MRC transfers the value in the register of the coprocessor to the register of the ARM processor.
MCR {<cond>} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm> {, <opcode2>}
MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm > {, <opcode2>}

MRC {< cond >} < coproc > ,< opcode_1>, < Rd >, < CRn > , < CRm > {,< opcode2 >}
MRC2 < coproc > ,< opcode_1>, < Rd >, < CRn > , < CRm > {,< opcode2 >}

<Rd>: ARM register, its value will be transferred to the register of the assistant sharp tool or read the value from the assistant processing register.
<CRn>: To assist the processor register
<CRm>: For additional destination register or source operand register.

Abnormal interrupt generation instruction

In the overview of ARM, we know that ARM has 7 modes, which can be divided into user mode and privileged mode. In privileged mode, you can access all resources of the system and switch to other modes at will. But in user mode, the authority is not so large, so what to do if you want to access system resources in user mode? ARM provides abnormal interrupt instruction SWI , through soft interrupt to realize the call to the privileged mode program in the operating system in user mode.
SWI {<cond>} <immed_24> The operating system distinguishes the type of service requested by the user program through a 24-bit immediate value.

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1. The instruction execution condition codes in ARM are as follows:
   ↩︎

2. Immediate data is 32bit, but not all operands are immediate data. Immediate number = 8-bit data >> Even number (up to 30 bits shift, some places say 32 bits, right shift 32 bits is actually no shift), the composition of the immediate number is the method that uses the least shift, so If the data width exceeds 8bit, it is definitely not immediate. Use the # mark for immediate data in the ARM instruction set . ↩︎

3. Arithmetic right shift is the sign bit, that is, the value of the highest bit is reserved; logical right shift is to fill the left-hand bit with 0; circular right shift is to fill the left-hand bit with the right-shifted bit; circular right shift with extension The most significant bit is filled with C bits in CPSR. ↩︎

4. F (full), E (empty): When the stack pointer points to the top element of the stack (the last data pushed onto the stack), it is called the full stack, and when the stack pointer points to an available data unit adjacent to the top element of the stack, it is called the empty stack. D (descending): The data stack grows in the direction of decreasing memory addresses, and A (ascending) data stack grows in the direction of increasing memory addresses. ↩︎