ARM instructions
1. ARM instruction set
1.1 Data processing instructions
Mnemonic |
operating |
Mnemonic |
operating |
MOV |
data transmission |
AND |
Logical and |
MVN |
Data inversion |
ORR |
Logical OR |
ADD |
plus |
EOR |
Logical exclusive OR |
ADC |
Add with carry |
BIC |
Bit clear |
SUB |
Less |
CMP |
Compare |
SBC |
Minus with borrow |
CMN |
Opposite number comparison |
RSB |
Reverse subtraction |
TST |
Bit test |
RSC |
Reverse minus with borrow |
TEQ |
Test for equality |
MOV R0, #0xFF
MOV R0, R0
MOV R0, R0, LSL#3
MOV PC, R14
MOVS PC, R14
MVN R0, #4
MVN R0, #0
ADD R0, R1, R2
ADD R0, R1, #0xFF
ADD R0, R2, R3, LSL#1
ADDS R0, R4, R8
ADCS R1, R5, R9
ADCS R2, R6, R10
ADCS R3, R7, R11
SUB R0, R1, R2
SUB R0, R1, #0xFF
SUB R0, R2, R3, LSL#1
SUBS R0, R0, R2
SBCS R1, R1, R3
RSB R2, R0, #0xFF
RSBS R2, R0, #0
RSC R3, R1, #0
AND R0, R0, #0x03
AND R2, R1, R3
AND R0, R0, #0x01
ORR R0, R0, #0x03
ORR R0, R0, #0x0F
EOR R0, R0, #0x03
EOR R1, R1, #0x0F
EOR R2, R1, R0
EORS R0, R5, #0x01
BIC R0, R0, #0x1011
BIC R1, R2, R3
CMP R1, #10
CMP R1, R2
CMN R0, #1
TST R0, #1
TEQ R0, R1
1.2 Multiplication instruction
Mnemonic |
operating |
Mnemonic |
operating |
I HAVE |
Multiply (preserve 32-bit result) |
UMLAL |
Unsigned long multiplication-accumulation |
MLA |
Multiply (32-bit result) |
SMULL |
Signed long multiplication |
UMULL |
Unsigned long multiplication |
SMLAL |
Signed long multiplication-accumulation |
MUL R1, R2, R3
MULS R0, R3, R7
MLA R1, R2, R3, R0
UMULL R0, R1, R5, R8
UMLAL R0, R1, R5, R8
SMULL R2, R3, R7, R6
SMLAL R2, R3, R7, R6
1.3 Jump instruction
Mnemonic |
operating |
Mnemonic |
operating |
B |
Jump |
BL |
Connection jump with return |
BX |
Jump and switch state |
BLX |
Jump with return and switch state |
B LABLE
B 0x1234
BL func
BX R14
1.4 Load/Store command
- Single register Load/Store instructions
Mnemonic |
operating |
Mnemonic |
operating |
LDR |
Load a word of memory into the register |
LDRBT |
Load a byte into the register in user mode |
STR |
Save the word in the register to the memory |
STRBT |
Save the lower 8 bits of the register to the memory in user mode |
LDRB |
Load a byte into a register |
LDRT |
Load a word into the register in user mode |
STRB |
Save the lower 8 bits of the register to the memory |
STRT |
Save words in memory to register in user mode |
LDRH |
Load a halfword into a register |
LDRSB |
Load a signed byte into the register |
STRH |
Save the lower 16-bit halfword in the register to the memory |
LDRSH |
Load a signed halfword into a register |
LDR R1, [R0, #0x12]
LDR R1, [R0, R2, LSL#2]
LDR Rd, [Rn], #0x04
STR R1, [R0]
- Load/Store instructions with multiple registers
Mnemonic |
operating |
Mnemonic |
operating |
LDM |
Load multiple registers |
STM |
Save multiple registers |
LDMIA R0!, {
R3~R9}
STMIA R1!, {
R3~R9}
STMFD SP!, {
R0~R7, LR}
LDMFD SP!, {
R0~R7, PC} ^
- Single data exchange instruction
Mnemonic |
operating |
Mnemonic |
operating |
SWP |
Word exchange |
SWPB |
Byte swap |
SWP R1, R1, [R0]
SWPB R1, R2, [R0]
1.5 Status register transmission command
Mnemonic |
operating |
Mnemonic |
operating |
MRS |
Send the program status register (PSR) value to the general register |
MSR |
Send the value of general register to PSR or send an immediate value to PSR |
MRS R1, CPSR
MRS R2, SPSR
MSR CPSR_c, 0xD3
MSR CPSR_cxsf, R3
1.6 Co-processing instructions
Mnemonic |
operating |
Mnemonic |
operating |
CDP |
Coprocessor data manipulation |
MRC |
Transfer data from coprocessor registers to ARM registers |
LDC |
Load coprocessor registers |
STC |
Store coprocessor registers |
MCR |
Transfer data from ARM register to coprocessor register |
|
|
1.7 Exception generating instructions
Mnemonic |
operating |
Mnemonic |
operating |
SWI |
Soft interrupt instruction |
BKPT |
Breakpoint interrupt instruction |
SWI 0
SWI 0x123456
2. ARM instruction addressing mode
2.1 Addressing mode of data processing instruction operand
The basic syntax format of ARM data processing instructions is as follows:
<opcode> {<cond>} {S} <Rd>, <Rn>, <shifter_operand>
- 立即数寻址:指令中的第二操作数<shifter_operand>是立即数
MOV R0, #0
ADD R3, R3, #1
CMP R7, #1000
BIC R9, R8, #0xff00
- 寄存器寻址:指令中的第二操作数<shifter_operand>是寄存器中的值
MOV R2, R0
ADD R4, R3, R2
CMP R7, R8
- 寄存器移位寻址:指令中的第二操作数<shifter_operand>是由寄存器中的值移位得到
ADD R2, R0, R1, LSR#5
MOV R1, R0, LSL#1
RSB R9, R5, R5, LSL#1
2.2 字及无符号字节的Load/Store指令的寻址方式
- 寄存器间接寻址:将地址放在一个通用寄存器中,即所需要的操作数保存在寄存器指定地址的存储单元中,即寄存器中的值为操作数的地址指针。寄存器间接寻址字及无符号字节的Load/Store指令语法格式如下示:
LDR|STR {<cond>} {B} {T} <Rd>, [Rm]
LDR R1, [R2]
STR R1, [R2]
- 基址变址寻址:是将基地址寄存器的内容与指令中给出的偏移量相加,形成操作数的有效地址。基址变址寻址的Load/Store指令语法格式如下示
LDR|STR {<cond>} {B} {T} <Rd>, [Rm, ±<addressing_mode>]
LDR R1, [R0, #0x0f]
STR R1, [R0, #-2]
STR R1, [R0, +R2]
2.3 批量Load/Store指令的寻址方式
- 多寄存器/块拷贝寻址:将一片连续内存单元的数据加载到通用寄存器组中或将一组通用寄存器的数据存储到连续的内存单元中。该类的指令语法格式如下示:
LDM|STM {<cond>} <addressing_mode> <Rn> { ! }, < registers/>< ^/>
STMIA R0!, {
R1-R7}
STMIB RO!, {
R1-R7}
STMDA R0!, {
R1-R7}
STMDB RO!, {
R1-R7}
- 堆栈操作寻址方式:对于堆栈的操作,数据写入内存和从内存中读出要使用不同的寻址模式,因为进栈操作和出栈操作要在不同的方向上调整堆栈操作
根据不同的寻址方式,堆栈可分为:Full栈、Empty栈、递减栈、递增栈
根据堆栈的不同种类,寻址方式可分为:满递减FD、空递减ED、满递增FA、空递增EA
2.4 相对寻址
相对寻址是基址寻址的一种变通,由程序计数器PC提供基准地址,指令中的地址码字段作为偏移量,两者相加后得到的地址即为操作数的有效地址。有 B 和 BL 指令
BL FUN1
B LOOP