A brief introduction to CPU registers and caches

A brief introduction to CPU registers

I have learned a lot of knowledge in this area recently, so I want to summarize it now.

In addition to devices such as controllers and arithmetic units, another important component of the CPU is the register. The function of the register is to temporarily store the data.

The operation speed of the CPU is very fast. For performance, the CPU opens up a small temporary storage area internally, and first copies the data from the memory to this small temporary storage area when performing the operation, and the operation is performed in this small temporary storage area. in the temporary storage area. We call this small temporary storage area a register.

The CPU read instructions are read from the memory. When an instruction is read and placed in the CPU, the CPU executes it. The reading speed of the memory is relatively slow, so the speed of reading from the memory determines the execution speed of the CPU. . So no matter how our CPU is upgraded, if the speed in this regard is not solved, its performance will not be greatly improved.

So in order to make up for this defect, a cache mechanism was added, and the A11 has only two levels of cache. This time can make up for the speed of memory read and write.

The faster the running speed, the more sophisticated the workmanship must be, so the cost will be higher, so the capacity must be limited.

Take the ARM processor A11 on the iPhoneX as an example. Its level 1 cache has a capacity of 64KB, and its level 2 cache has a capacity of 8M.

When we read the instruction, we will execute whoever the PC register points to, and then the CPU will first look for the mapping table. If it finds that there is this address in the cache, it will go to the cache to read.

If the address pointed to by the PC cannot be found in the cache, it will go to the memory to find it, and then according to a specific replacement strategy, the instructions or data in the memory will be copied to the memory.

The cache memory is a first-level memory that exists between the main memory and the CPU, and is composed of static memory chips (SRAM).

It mainly consists of three parts:

  • Cache bank: Stores instructions and data blocks called from main memory

  • Address translation component: build a directory table to realize the translation of main memory address to cache address

  • Replacement component: When the cache is full, the data block is replaced according to a certain strategy, and the address translation component is modified

About the introduction of static memory chips:

Static Random-Access Memory (SRAM) is a type of random access memory. The so-called "static" means that as long as the memory is kept powered on, the data stored in it can be kept constantly. In contrast, the data stored in dynamic random access memory (DRAM) needs to be updated periodically.

About the specific difference between static memory chips and dynamic random access memory

SRAM does not require a refresh circuit to preserve its internally stored data. DRAM (Dynamic Random Access Memory) needs to be refreshed and charged every once in a while, otherwise the internal data will disappear, so SRAM has high performance and low power consumption, but SRAM also has its shortcomings, that is, its integrated The DRAM memory of the same capacity can be designed in a smaller volume, but the SRAM requires a large volume. The same area of ​​silicon can make a larger capacity DRAM, so SRAM is more expensive.

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