This article describes how to configure a 40MHz core freqency KEAZ128 Evaluation Edition (FRDM-KEAZ128Q80) / 20MHz bus frequency.
1. To understand the characteristics of the device clock
See KEA128 DS NXP ( S9KEA128P80M48SF0.pdf ), you can know this MCU supports up to 48MHz core frequency.
RM from KEA128 ( KEA128RM (Chinese) .pdf ), you can name and know KEA128 each clock frequency and other characteristics. It should be noted that the configuration the core clock frequency (40MHz) must be less than the maximum frequency (48MHz). Since the external clock more stable internal clock, and reliable, so selecting the external crystal as the bus clock source.
However, why the core frequency is the highest frequency of 48MHz? 8MHz external crystal frequency up how much support it? Read on.
3. Observe a block diagram of a clock, the clock select a route configuration
From RM clocking scheme can see various types and connection relationship KEA clock,
If the IRC = 37.5KHZ to as FLL reference clock, multiplier FLL = 1280, then the core clock = 37.5KHZ * 1280 = 48000KHZ = 48MHZ. This explains how the calculation is the maximum frequency of 48MHZ come.
However, the desired, rather than using the IRC internal clock, but the external crystal (8MHz) as the clock source should be selected so that following this route configuration.
4. Calculate the required configuration parameters and clock
From the above roadmap know to use 8M generates 40MHz, FLL frequency must be (1280 *), and 8M * 1280 = 10240M >> 48M, obviously unreasonable, it will not be sent directly to 8M FLL input must be after performing the division process module through the system oscillator (OSC), in order after FLL frequency.
Provided OSC division factor = n, then the core clock = 8M / n * 1280 / bdiv / div1, where n belongs to the OSC module, bdiv ICS belonging module, SIM module DIV1 belongs.
However, OSC is what modules? What is the relationship with ICS?
5. Analysis module internal clock source (ICS)
See section RM ICS, can be found as follows select line configuration ICSOUT (ICSOUTCLK), and further arranged core clock. Here the external reference clock input, a frequency divider RDIV be determined, then the FLL frequency, then the frequency division BDIV give ICSOUT.
1) take a look at RDIV, how is the division of.
See register described, can be known, the RDIV division, (frequency range) associated with OSC_CR [RANGE]. 8M external crystal oscillator as the clock OSC module (8M> 4M), the inevitable choice OSC_CR [RANGE] = 1, that is, the frequency division factor can only be represented RDIV 32, 64, ... 1024.
Try RDIV = 0b000, which is rdiv = 32, then the core clock = 8M / 32 * 1280 / bdiv / div1 = 320M / bdiv / div1, in theory, you can set bdiv * div1 = 8, so that the final core clock of 40MHz , but the process will result in the transmission of the clock 8M / 32 * 1280 = 320M, which may cause the device from a variety of normal.
When configuring the clock, not only to meet the end result is less than the maximum clock, and the clock in the process, it must comply with the specifications manual. Here, the selection RDIV = 0b011 => rdiv = 256, the core clock = 8M / 256 * 1280 / bdiv / div1 = 31.25kHz * 1280 / bidv / div1 = 40M / bdiv / div1, where FLL output as 40M, 40M is in line ~ 50M required.
FLL output request <50M
2) look at is how the division of BDIV
Directly determined by setting 0 ~ 0b111.
