STM32H7 clock tree RCC analysis---principle explanation (1)

There are many series of STM32, which can meet the various needs of the market. From the core, there are Cortex-M0, M3, M4 and M7. Each core is roughly divided into mainstream, high performance and low power consumption.

For configuration with HAL library, please see: STM32H7 Clock Tree Analysis - HAL Library Configuration (2)

F1 represents the basic type, based on the Cortex-M3 core, the main frequency is 72MHZ, F4 represents the high performance, based on the Cortex-M4 core, the main frequency is 180M, and F7 represents the high performance, based on the Cortex-M7 core, the main frequency is 216M. H7 represents ultra-high performance, based on Cortex-M7 core, clocked at 400M

Today we are talking about this MCU of the STM32H7 ultra-high performance series

If you are a beginner, it is recommended to read this first, you will have a basic understanding of the clock tree
[STM32] Detailed explanation of system clock RCC (super detailed, super comprehensive)

First of all, let's take a look at the clock tree of H7. At first glance, it is very big, and there are too many things more than F1. Let's take a closer look and find that there are still many. Don't worry, then I will show you the overall clock tree. Principles and analysis of each module.

Because the overall block diagram is too large, we divide it into several parts to analyze, first look at the external input clock source :

external clock source

STM32H7 has a total of 6 external clock sources, which are:

• HSI (High Speed ​​Internal Oscillator) Clock: ~ 8 MHz, 16 MHz, 32 MHz, or 64 MHz
• HSE (High Speed ​​External Oscillator) Clock: 4 MHz to 48 MHz
• LSE (Low Speed ​​External Oscillator) Clock: 32 kHz
• LSI (Low Speed ​​Internal Oscillator) Clock: ~ 32 kHz
• CSI (Low Power Internal Oscillator) Clock: ~ 4 MHz
• HSI48 (High Speed ​​48 MHz Internal Oscillator) Clock: ~48 MHz

LSI

LSI belongs to the STM32H7 internal low-speed clock source with a frequency of about 32Khz.

• LSI can keep running as a low power clock source for independent watchdog (IWDG) and RTC clock/auto-wake-up unit (AWU)

LSE

LSE is an external low-speed clock source , usually 32.768Khz (generated by a 32.768Khz crystal or ceramic resonator)

• Can be used as a real-time clock (RTC) clock source to provide clock/calendar or other timing functions with low power consumption and high accuracy

HSE

HSE is an external high-speed clock. Normally, we use HSE as the system clock input, and a 25Mhz external crystal oscillator is commonly used .

• HSE is automatically disabled by hardware when the system enters stop or standby mode
• The HSE clock can be driven to the MCO1 and MCO2 outputs and used as a clock source for other application components

HSI

HSI is an internal high-speed clock with a frequency of 64Mhz;

• Can be used directly as system clock, peripheral clock or PLL input
• Selectable HSI output frequency of 8 MHz, 16 MHz, 32 MHz or 64 MHz using HSIDIV prescaler

CSI

CSI is a low-power internal clock with a frequency of 4Mhz;

• Can be used directly as system clock, peripheral clock or PLL input
• The frequency of CSI is extremely low. Even after frequency calibration, the frequency of CSI is not as high as the frequency accuracy of external crystal oscillator or ceramic resonator, and its advantage is low power consumption.

CSS (Clock security system)

The clock security system, that is, the monitoring system, the two external clock sources of the H7, HSE and LSE, have security monitoring. Once enabled, if the HSE or LSE fails to start, the system clock will switch to the HSI. If the interrupt is enabled, the non-maskable interrupt NMI will be entered.

HSI48

HSI48 is an internal high-precision clock source with a frequency of 48Mhz;

• It provides a 48 MHz clock that can be used directly as a core clock for some peripherals
• Mainly used as a clock source for USB peripherals through a special Clock Recovery System (CRS) circuit

Ok, through the above introduction, you should understand several major clock sources of H7, then where will these clock sources be used in the future, let's analyze it again

IWDG ， RTC ， AWU

The part of the violet box in the upper half is the independent watchdog (IWDG) and the RTC clock/automatic wake-up unit (AWU)

• Independent Watchdog (IWDG) can only be provided by LSI

• RTC and AWU can be divided by 1M of LSE LSE and HSE as clock source

Phase Locked Loop PLL

PLL (Phase Locked Loop): Phase Locked Loop or Phase Locked Loop. In general, it plays the role of frequency doubling of the crystal oscillator frequency, which improves the necessary conditions for the high-speed operation of the system.

VCO (voltage-controlled oscillator): a voltage-controlled oscillator, which is a component of the PLL. The

STM32H7 has three PLL phase-locked loops:

• One main PLL (PLL1) , typically used to clock the CPU and certain peripherals.
• Two dedicated PLLs (PLL2 and PLL3) are used to generate core clocks for peripherals.

The input clock source to the PLL is refx_ck , and the frequency of the reference clock (refx_ck) provided to the PLL must be in the range of 1 MHz to 16 MHz

Among them, the three clock sources of HSI CSI HSE can be used as input, and then pass through the PLL clock source selector PLLSRC , which mainly selects which oscillator to use as the clock source, and then divides the frequency by DIVMx to obtain a clock frequency of 1 MHz to 16 MHz. We generally choose the PLL clock source from hse_ck , usually 25Mhz

DIVMx: PLLx clock source prescaler, used to divide the frequency of the clock source selected by PLLSRC, the value range is: 2~63

PLL1

PLL1 phase-locked loop, the PLL mainly uses two outputs: pll1_p_ck and pll1_q_ck, among which: pll1_p_ck is generally used as the clock source of the sys_ck system clock , and finally used as the clock source of CPU, SysTick, AXI, AHB1~4 and APB1~4, etc. ; and pll1_q_ck can be selected as the core clock (perx_ker_ck) of some peripherals through PKSU, such as FMC, QSPI, SDMMC1/2, etc. As for the pll1_r_ck in the figure, it is not used.

• DIVN1 is the frequency multiplication factor of the main PLL1 vco, and its value range is: 4~512;
• DIVP1 is the P frequency division of PLL1, which is used to obtain the frequency of pll1_p_ck, and its value range is: 2, 4, 6...128 (must be an even number);
• DIVQ1 is the Q frequency division of PLL1, and its value range is: 1~128;
• DIVR1 is not used;
• FRACN1 is a fractional frequency multiplication factor, which together with DIVN1 constitutes the frequency multiplication factor of PLL1, but we generally do not need to use fractional frequency multiplication

Taking pll1_p_ck as an example, here is a brief introduction to the calculation formula of the PLL output frequency (the clock PLL input frequency is hse_ck):

Assuming that the external crystal oscillator is 25Mhz, we need to get the pll1_p_ck frequency of 400Mhz as the system clock, then you can set: DIVM1=5, DIVN1=160, DIVP1=2

PLL2 and PLL3 are similar to PLL1, and we will not repeat them here.

system clock

After a system reset, HSI is automatically selected as the system clock and all PLLs are turned off. , that is, every time the system is reset, the HSI will be used as the system clock . When the system is stable, PLL1 can be configured, and the system clock can be switched to plll1_q_ck (400Mhz) to get the highest performance.

当时钟源用于系统时钟时，软件无法关闭所选时钟源，也就是系统时钟软件无法禁止

• SCGU (System Clock Generation Unit) is used to divide sys_ck into various
  clock frequencies, such as CPU frequency, SysTick, AXI, AHB1~4 and APB1~4.
• SCEU (System Clock Enable Unit) is used to enable the clocks of various peripherals, buses, etc., and is a clock switch.

Let's give a detailed introduction to the generation of the system clock:

The above figure mainly lists the generation principle of the STM32H743 system clock, including the CPU clock, SysTick clock, AXI clock, AHB1~4 and APB1~4, etc. It is very important for system operation. In the figure, D1, D2 and D3 domains are 3 independent power domains designed by ST to support dynamic energy efficiency management, and each domain can be turned on/off independently. The system clock is generated by SCGU, then switched by SCEU, and finally output to each clock domain (D1, D2, and D3), so that various peripherals can be controlled and accessed to ensure the normal operation of the system.

1. SCGU input clock (sys_ck) , the clock we generally choose from pll1_p_ck, the frequency is 400Mhz
2. DICPRE : The frequency division factor of sys_d1cpre_ck clock , the value range is 1~512, set by the D1CPRE[3:0] bits of the RCC_D1CFGR register, we generally set the frequency division to 1 to get the highest sys_d1cpre_ck frequency, 400Mhz
3. After frequency division by HPRE, it is used for peripherals such as AXI clock. Note that the highest frequency here is 200Mhz, that is, the highest frequency of most peripherals is 200Mhz , so when sys_ck is 400Mhz, HPRE is at least divided by 2.
4. Used as a clock for HRTIM, the frequency can reach 400Mhz
5. CPU clock (rcc_c_ck, rcc_fclk_c) , the CPU clock is directly from sys_d1cpre_ck, there is no divider, the frequency is 400Mhz
6. SysTick clock divider (fixed divided by 8), this is wrong in the figure, in fact, this divider is not (hardware bug), so the clock frequency of SysTick comes directly from sys_d1cpre_ck, the frequency is 400Mhz system clock
7. Enable unit (SCEU) , it can control on/off all peripheral clocks in D1, D2 and D3 domains, so when using peripherals, you must set SCEU to enable its clocks, otherwise the peripherals cannot be used, That is to configure the enable ENR of each peripheral clock
8. D1 domain , is a high-performance domain, mainly for CPU clock and AXI peripherals, AHB3 peripherals
9. The D2 domain , the communication interface domain, is mainly used for data communication to reduce the burden on the CPU. This field includes: AHB1, AHB2, APB1, and APB2 clock parts.
10. D3 domain , data batch domain, this domain includes clock parts such as AHB4 and APB4

MOC1 / MOC2

Two clock output (MCO) pins are available, MCO1 and MCO2. A clock source can be selected for each output.

• GPIO ports must use MCO in alternate function mode.
• The clock frequency provided by the MCO output cannot exceed the maximum pin speed
• MCO1 can be output on PA8 pin
• MCO2 can be output on PC9 pin

PKSU/PKEU

SCEU : Access clock for controlling peripherals (access registers)
PKEU: Core clock for controlling peripherals (generating control timing, such as baud rate, etc.)

Not all peripherals need to use PKEU, because some peripherals do not need to generate timing, there is no so-called peripheral core clock, such as DMA, OPAMP, etc. These peripherals only need to be enabled in SCEU

The following figure is a detailed peripheral clock enable block diagram

SCGU and SCEU in the first half have already been discussed, here we only talk about the second half:

• Peripheral kernel clock selection unit (PKSU, namely: Peripheral Kernel clock Selection Unit) , used to
  select the kernel clock source of a peripheral, the specific selection relationship.
• Peripheral kernel clock enable unit (PKEU, namely: Peripheral Kernel clock Enable Unit) , this part
  enables/disables the peripheral kernel clock selected at PKSU, and finally controls whether to output the kernel clock (rcc_perx_ker_ck) to the peripherals.
• Kernel Control Logic (Kernel Control Logic) is used to control whether PKEU outputs the core clock to the peripherals. It has many control signals, of which we commonly use PERxEN. The setting of this bit can control the on/off of the specific peripheral core clock. close.
• Peripheral core clock (rcc_perx_ker_ck) , this clock is used to drive peripherals to generate timing, such as baud rate, clock pulse, etc. Most peripherals need to use rcc_perx_ker_ck, such as serial port, SPI, IIC, FMC, SAI, LTDC and CAN.

---

Here is a very good block diagram in the data sheet of STM32H7 (you can find it by searching Figure 1 in the data sheet), you can have an intuitive understanding of the overall architecture of H7, and you can see the bus connected to each peripheral, and the maximum clock frequency of each bus.

AHB (Advanced High-performance Bus)
APB (Advanced Peripheral Bus) Advanced Peripheral Bus
AXI (Advanced eXtensible Interface) Advanced Extensible Interface

AHB is mainly designed for high-efficiency, high-bandwidth and fast system modules. It can connect high-efficiency modules such as microprocessors, on-chip or off-chip memory modules and DMA.

APB is mainly used in low-speed and low-power peripherals, and can optimize power consumption and complex interfaces for peripheral devices. APB provides a communication bridge between AHB and low-bandwidth peripheral devices, so APB is a secondary expansion bus of AHB or ASB.

AXI: high speed, high bandwidth, pipelined interconnection, one-way channel, only the first address is required, parallel reading and writing, support for out-of-order, non-aligned operations, effective support for peripherals with high initial delay, and many connections.

Together, these define a set of standards for on-chip communications designed for high-performance SoCs.

For example, you can see that SYSCLK(Hz) = 400MHz (CPU Clock) and you will know the error at the beginning of the above CPU block diagram

It can be seen that a 64bit AXI BUS and a 32bit AHB BUS are attached to the CPU

FLASH FMC QSPI These are the
commonly used TIM UART SPI IIC on the AXI bus hanging on the AHB bus

The 64-bit AXI bus has a 32-bit AHB4, etc.

The lower right corner is the block diagram of the clock, you can see the RTC clock watchdog clock

It can be seen that the clock of the HSE is 4-48Mhz, and then the APB4 bus is plugged in through three PLL phase-locked loops and then externally output

. For example, the 200Mhz AHB4 is divided to generate the APB4 highest bit 100Mhz.

• APB1 timers include TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14, LPTIM1
• APB2 timer has TIM1, TIM8, TIM15, TIM16, TIM17
• LCD-TFT FIFO on APB3
• APB4 timer has LPTIM2, LPTIM3, LPTIM4, LPTIM5

---

There is also the following bus system framework.

It can be clearly seen that the peripherals are divided into three domains: D1 Domain, D2 Domain and D3 Domain.
◆ D1 Domain
The peripherals in the D1 domain are linked to the 64-bit AXI bus to form a 6*7 matrix.

6 slave interfaces ASIB1 to ASIB6

• The external masters are LTDC, DMA2D, MDMA, SDMMC1, AXIM and D2-to-D1 AHB bus.

7 main interface terminals AMIB1 to AMIB7

• The external slave devices are AHB3 bus, Flash A, Flash B, FMC bus, QSPI and AXI SRAM.
• AHB3 is also branched from the AXI bus, and then the APB3 bus is branched from AHB3.

◆ D2 Domain
The peripherals of the D2 domain are connected to the 32-bit AHB bus to form a 10*9 matrix.

• The 10 slave interface external masters are D1-to-D2 AHB bus, AHBP bus, DMA1, DMA2, Ethernet MAC, SDMMC2, USB HS1 and USB HS2.

• The slave devices connected to the 9 master interfaces are SRAM1, SRMA2, SRAM3, AHB1, AHB2, APB1, APB2, D2-to-D1 AHB bus and D2-to-D3 AHB bus.

◆ D3 Domain

The peripherals of the D3 domain are linked to the 32-bit AHB bus to form a 3*2 matrix.

• 3 external masters D1-to-D3 AHB bus, D2-to-D3 AHB bus and BDMA.
• The external slave devices of the 2 master interfaces are AHB4, SRAM4 and Bckp SRAM. In addition, AHB4 is also branched from this bus matrix, and then APB4 bus is branched from AHB4.

For configuration with HAL library, please see: STM32H7 Clock Tree Analysis - HAL Library Configuration (2)