STM32H5 Development (3)----Power Control & RCC

STM32H503 power supply

VDDA = 1.62 V ~3.6 V : External power supply for ADC/DAC
VDDIO2 = 1.08 V ~ 3.6 V : External power supply for 9 I/Os (PA8, PA9, PA15, PB3:8) (WLCSP25 package only) VDD =
1.71 V ~ 3.6 V: GPIO, internal voltage modulator, system reset module, power management and external power supply for internal clock
VBAT = 1.2 V ~ 3.6 V: Power switch for RTC/internal 32kHz oscillator (LSI) when there is no VDD /Backup domain register/Optional backup SRAM power supply.
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sample application

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STM32H562/563/573 LDO power supply

VDDA = 1.62 V (ADCs, DACs) / 2.1 V (VREFBUF) ~ 3.6 V
VDDIO2 = 1.08 V ~ 3.6 V : External power supply for 10 I/Os (PD6, PD7, PG9:14, PB8, PB9) VDD
= 1.71 V ~ 3.6 V
VBAT = 1.2 V ~ 3.6 V
VDDUSB = 3.0 V ~ 3.6 V
VDDUSB Independent USB power supply.
VDDUSB is independent of VDD, and the level can be different. When the USB is not used, VDDUSB must be connected to VDD.

STM32H562/563/573 SMPS power supply

VDDA = 1.62 V (ADCs, DACs) / 2.1 V (VREFBUF) ~ 3.6 V
VDDUSB = 3.0 V ~ 3.6 V
VDDIO2 = 1.08 V ~ 3.6 V : 10 I/Os (PD6, PD7, PG9:14, PB8, PB9) The external power supply
VDD = 1.71 V ~ 3.6 V
VBAT = 1.2 V ~ 3.6 V
VDDSMPS = 1.71 V ~ 3.6 V
VLXSMPS is the output pin of SMPS, which is connected to VCAP after filtering.

LDO/SMPS power supply

In bypass power supply mode, Vcap must rise above 1.1V before VDD reaches the POR voltage value, and only after the LDO is disabled can the external Vcap voltage be adjusted according to the application requirements.

PWR characteristics

The figure below shows the power supply comparison between the STM32H5 128K and 2M mcu.

Supply voltage monitoring

Since there are many external power supply pins, a problem with any one power supply may cause the MCU to fail to work properly. Therefore, in order to ensure the normal operation of the MCU in H5, a variety of power supply voltage monitoring functions are added to the system, as follows.

temperature monitoring

The temperature sensing function uses a dedicated temperature sensor on the chip to detect the temperature change of the chip. This function can be enabled through an on-chip register. Once enabled, when the temperature is higher than 126°C or lower than -37°C, the corresponding flag bit will be set, and an intrusion event or wakeup interrupt may be triggered at the same time. When the temperature returns to the normal range, the flag will be cleared normally.

low power mode

• STM32H5 series MCUs include 3 low power consumption modes:
❖ SLEEP mode
❖ STOP mode
❖ STANDBY mode

• VBAT mode:
When VDD is powered off, but VBAT is powered, the hardware will automatically start

Low power consumption mode - SLEEP mode

• CPU clock is stopped, all peripherals and CortexM33 core including NVIC, SysTick can run, and wake up CPU when events and interrupts occur • Wakeup
source: any interrupt or wakeup event
• Wakeup system clock: same as before entering Sleep mode
• Voltage Regulator range: VOS3, VOS2, VOS1 or VOS0

Low Power Mode - STOP Mode

• All clocks in the core domain are stopped, PLL, HSE, HSI (unless HSIKERON is set), HSI48 and CSI (unless CSIKERON is set) are disabled • RTC
can keep working (RTC can be selected in Stop mode)
• Exit Stop mode After that, the system clock is HSI or CSI, depending on the software configuration
• Wake-up source: any peripheral event specified by the EXTI line (configured through the EXTI register)
• Wake-up clock: When STOPWUCK = 1 in RCC_CFGR, the clock after wake-up is CSI; STOPWUCK = 0, the wake-up clock is HSI, the frequency is the same as when entering Stop mode, up to 64Mhz
low power mode-STOP mode
• LSE or LSI keeps working
• Voltage regulator range: SVOS3, SVOS4, or SVOS5

Low power mode - STANDBY mode

• The voltage regulator is turned off and the core domain is completely powered down
• PLL, HSI, HSI48, CSI, HSE are all turned off
• The contents of SRAMs and registers are lost, except for the registers and SRAM of the backup domain and the Standby circuit
• RTC can keep working (in Standby mode You can choose whether RTC works)
• BOR keeps working in Standby mode
• I/O status can be kept in Standby mode
• Wake-up source: wake-up pin WKUPx edge signal, RTC event, external NRST pin reset, independent watchdog reset ( IWDG), BOR
• Wake-up clock: HSI clock at 32 MHz
• Voltage regulator: OFF

Low Power Mode Monitor Pins

(1) PWR_CSLEEP AF is mapped to PC3
(2) PWR_CSTOP AF is mapped to PC2
(3) CSLEEP and CSTOP signals are generated by Vcore domain, so this signal cannot be obtained in Standby mode

VBAT mode

• The backup domain contains:

• RTC (clocked by LSE (32.768kHz))
• Intrusion detection pin
• backup domain register
• RCC_BDCR Register
• Backup SRAM (if backup voltage regulator is enabled)

• VDD power down and power up, internal switch automatically switches between VDD and VBAT

• Switching to VBAT power supply mode is controlled by the power-down reset in the reset module

• Internally connected to ADC for voltage sensing (VBAT/4)

• VBAT battery charging

• If VDD is normal, the external battery on the VBAT pin can be charged through the internal resistor
• Set the VBE bit in the PWR_BDCR register to enable the charging function
• In VBAT mode, the charging function is disabled by default

Reset trigger source

clock source

Clock tree (simplified)

Clock output Clock-out

HSI & CSI

• HSI is the default clock after system reset, the default configuration is 32 MHz.
• CSI@4MHz and HSI@64MHz, factory/user calibration
• By STOPWUCK bit, CSI or HSI can be selected as:

• Clock after wake-up from STOP mode
• CSS (Clock Security System) backup clock

• Can be started automatically after exiting STOP mode

• Configure CSI or HSI start via STOPWUCK

• Can keep working in STOP mode to achieve fast wake-up (set CSIKERON/HSIKERON)
• In STOP mode, some peripherals can enable CSI or HSI when they need clocks to detect wake-up events
Note: After exiting STANDBY mode, HSI 32Mhz

Peripheral Core Clock Request

• Peripherals with core clock request capability:
• I3C
• I2C
• USART
• LPUART
• After receiving the request, RCC enables the core clock (for example CSI or HSI)

Clock Security System (CSS)

• CSS for HSE

• Only available in RUN/SLEEP mode
• If clock failure is detected
  1. The system clock is switched to HSI or CSI according to user configuration
  2. Trigger NMI
  3. Trigger Tamper
  4. The event is related to the Break input of advanced timing

• CSS for LSE

• VBAT mode available
• To detect clock loss or abnormal frequency, software is required for RTC clock switching (LSI/HSE)
• CSS heartbeat connected to tamper3
• The interrupt used is the TAMP interrupt

Note: If LSE CSS is triggered: Tamper-protected areas (including SRAM2) cannot be accessed until the Tamper flag is cleared by software