Clock Trees and Skew Groups
Clock trees and skew groups are the two key object types used in the CCOpt clock specification. The term object is used here
because clock tree and skew group objects can be defined, modified, and deleted using commands. For example,
create_ccopt_clock_tree , create_ccopt_skew_group , modify_ccopt_skew_group , and delete_ccopt_skew_groups .
Properties can be set per skew group or clock tree instead of globally.
For example,
set_ccopt_property
–skew_group name
target_skew value .
The report_ccopt_clock_trees and report_ccopt_skew_groups commands can be used to generate reports on clock trees and
skew groups. For more information, see the Reporting section.
Clock Trees
The union of all clock trees specifies the subset of the circuit graph that CTS will buffer. The circuit subset covered by clock tree
definitions is best referred to as a clock tree graph since clock trees may interact, for example via clock logic cells. The clock
tree graph is a single physical graph even in a multi-mode timing environment.
Maximum transition times, route types and other physical properties are associated with the clock tree graph or with individual
trees in the clock tree graph.
In all but rare exceptional circumstances, the clock tree definitions created by create_ccopt_clock_tree_spec do not require
user modification.
Skew Groups
A skew group represents a balancing constraint and is the CTS equivalent of an SDC clock. The automatically generated clock
tree specification will create one skew group per SDC clock per mode.
Each skew group has one or more sources and a number of sinks. Among other properties, a skew target and insertion delay
target can be set per skew group. Any pin in the clock tree graph can be a skew group source or sink and pins can be
designated a skew group specific ignore pin such that the specific skew group does not propagate beyond the pin.
CCOpt-CTS global skew balancing aims to achieve an equal delay, subject to the skew target, from all sources to all sinks
within each skew group. CCOpt virtually balances skew groups to zero skew to determine initial clock tree timing with
propagated clocks before optimization starts.
A skew group can be viewed as a subset of the clock tree graph superimposed on top of the clock tree graph. Skew groups can
overlap, share sources, and/or sinks.
In complex cases or with CCOpt-CTS where the SDC timing constraints do not fully capture the balancing requirements, user
adjustment to the skew group configuration may be required and/or additional skew groups can be defined.
Network Latencies
The create_ccopt_clock_tree_spec command will translate clock network latency settings to an insertion delay target on the
corresponding skew group. For example, consider the functional mode SDC constraint, “set_clock_latency 1.456 [get_clocks
{ck1}]”. The automatically generated specification will contain the following line:
set_ccopt_property target_insertion_delay -skew_group ck1/func 1.456
Similarly, pin network latency settings are translated to the insertion_delay property of a pin. This property is often referred to as a
pin insertion delay. A pin insertion delay represents the delay ‘underneath’ a clock sink. For example, for a macro clock input pin, the
pin insertion delay would represent the internal clock path delay inside the macro. Continuing the above example, add the constraint
“ set_clock_latency 0.234 [get_pins {mem1/CK}] ”. The automatically generated specification will additionally contain the
following line:
set_ccopt_property
insertion_delay
–pin mem1/CK 1.222
The property setting indicates that the delay internal to the macro clock input mem1/CK is 1.222 . The value 1.222 is computed as
the difference between the clock latency of 1.456 and the pin latency of 0.234 . Note that SDC pin-specific latencies override clock
latencies, which means they are not added together.
Clock Tree Convergence
In some circumstances, the clock tree graph undesirably propagates into datapath and includes what should be datapath as part of
the clock tree graph. For example, this can happen due to missing set_case_analysis or other incorrect SDC constraints. Including
significant datapath logic as part of the clock tree graph can result in excessive CCOpt or CCOpt-CTS run time due to large numbers
of paths existing between a skew group source and sink due to multiple levels of re-convergent logic. Additionally, such paths would
not be optimized by datapath optimization.
To help detect cases where run time would be adversely affected, the automatically generated clock tree specification includes an
invocation of the check_ccopt_clock_tree_convergence command. This command traces the number of paths to every sink and
issues a warning if the number of clock paths to any sink is greater than a default threshold of 100 paths. The
report_ccopt_clock_tree_convergence command can be used to report sinks with large numbers of clock paths.
To remedy this situation, either correct the SDC constraints, for example by adding set_case_analysis , set_clock_sense –
stop_propagation or other suitable commands, or use a clock tree stop, ignore, or exclude pin as appropriate. These pins are
described in the next section.
Clock Tree Sink Pin Types
Clock tree sink pin types can be manually overridden before invoking the create_ccopt_clock_tree_spec command with the
following property setting:
set_ccopt_property –pin
pin_name
sink_type ignore | stop | exclude
Clock tree sink pin types can be manually overridden before invoking the create_clock_tree_spec command with the following
attribute setting:
set_db pin:name .cts_sink_type ignore | stop | exclude
Ignore pin (ignore)
An ignore pin is considered as a part of the clock tree graph. CTS will perform DRV buffering up to the pin, but the pin will not be
considered as a sink in any skew group, which means the latency to an ignore pin is not important. Tracing through and beyond the
pin will be disabled. Sometimes such a pin is referred to as a clock tree ignore pin. An alternative strategy to deploying an ignore pin
would be to use the SDC constraint, set_clock_sense –stop_propagation. This may be preferable since it would keep the timing
model in synchronization with the CTS configuration.
Stop pin (stop)
A stop pin is considered as a part of the clock tree graph. CTS will perform DRV buffering up to the pin and by default the pin will be
considered a sink to be balanced in any skew group that reaches the stop pin. Tracing through and beyond the pin will be disabled.
Exclude pin (exclude)
An exclude pin is a pin that is not part of the clock tree graph but might still be connected to a clock net anyway if the same net has
other clock fanout. Specifically, the clock tree graph must not extend beyond an exclude pin but it can be pruned back from an
exclude pin. The create_ccopt_clock_tree_spec command will prune back from an exclude pin and, if possible, specify an ignore
pin earlier in the fanin cone. The Shared Clock and Data Concerns section discusses how to add buffers to disconnect exclude pins
from any clock tree nets they may be connected to. This can be important where clock and datapath overlap.
Note: In addition to the above pin types, it is possible to make any pin that is within the clock tree graph a skew group specific ignore
or sink pin. This is discussed in the subsequent sections.
Manual Setup and Adjustment of the Clock Specification
Following are some important recommendations for setting up and adjusting the clock tree specification:
It is recommended that the create_ccopt_clock_tree_spec command is used to create the clock tree specification.
It is not recommended to edit the specification file generated by the create_ccopt_clock_tree_spec -file filename
command. A more stable flow is obtainable either by adjusting the SDC, configuring CCOpt properties, setting clock tree sink
pin types before generating the specification, or making skew group adjustments after loading the specification.
Consider making adjustments to the SDC timing constraints instead of the CTS specification, if applicable. This will ensure that
timing analysis uses a clock propagation model consistent with the CTS configuration. For example, setting a clock logic
instance input pin to be a clock tree ignore pin will stop CTS tracing through the pin, but will not stop report_timing from
propagating a clock through the pin. The create_ccopt_clock_tree_spec command has been engineered to create a clock tree
specification consistent with the active timing constraints.
The table below shows commonly used commands for manipulating clock trees and skew groups:
Defining Clock Trees
Clock trees are defined using the create_ccopt_clock_tree and create_ccopt_generated_clock_tree commands. For example:
create_ccopt_clock_tree -name ck -source ck -no_skew_group
create_ccopt_generated_clock_tree -name gck -source d1/Q -generated_by d1/CK
The optional -name parameter can be used to specify the name of the clock tree. Alternatively, the source pin name will be used as
the clock tree name. The mandatory -source parameter specifies the clock tree root pin from which clock tree tracing will be
performed. The -no_skew_group parameter disables the automatic creation of a corresponding skew group, otherwise a skew group
with the same name as the clock tree is automatically created. In addition, the definition of a generated clock tree requires the -
generated_by parameter to specify the input side of the clock generator, which is typically the clock input pin of a divider flip-flop.
When a clock tree is defined, CCOpt traces the circuit connectivity from the specified source pin, adding the nets and cell instances it
encounters to the clock tree graph. Tracing continues until encountering a clock pin (such as a flip-flop, latch, or macro input), a user-
defined stop, ignore, or exclude pin. A generated clock tree definition must normally be used at the output of a sequential cell to
continue tracing.
Defining Skew Groups
Skew groups are defined using the create_ccopt_skew_group command. The complete syntax of this command is detailed below:
create_ccopt_skew_group
[-help]
[-constrains cts | ccopt_initial | ccopt | subset_of_values | all | none]
[-from_clocks clock_names]
[-from_constraint_modes constraint_mode_names]
[-from_delay_corners delay_corner_names]
-name skew_group_name
[-rank rank]
[-sinks pins | -shared_sinks pins | -exclusive_sinks pins | -auto_sinks | -filtered_auto_sinks pins | -
balance_skew_groups skew_groups]
[-sources pins | -balance_skew_groups skew_groups]
[-target_insertion_delay value]
[-target_skew value]
Note: The parameters taking a list of pins operate with either a plain TCL list of hierarchical pin names or with a collection of pins
obtained from the get_pins command.
Skew Group Rank
The rank of a skew group determines whether a sink pin is an active sink in that skew group or not. A pin is only an active sink in the
skew group(s) with the highest rank out of all the skew groups to which the pin belongs. An active sink is a pin that will be balanced
against other active sinks in the same skew group.
For example, consider the following sequence of commands:
create_ccopt_skew_group -name SG1 -sources get_pins top -shared_sinks [get_pins */D]
create_ccopt_skew_group -name SG2 -sources get_pins top -exclusive_sinks [get_pins XYZ/D]
create_ccopt_skew_group -name SG3 -sources get_pins top -exclusive_sinks [get_pins XYZ_01/D]
After running the first command, a single skew group SG1 is created. Shared sinks are specified so this skew group has a rank of
zero. All the “D” pins in the design are members of this skew group. In addition, all the “D” pins are active sinks in skew group SG1.
This is because SG1 is the highest ranked skew group so far, even though it has a rank of zero.
The second command defines skew group SG2. Exclusive sinks are specified so this skew group has a rank of 1, which is one
higher than the current highest rank of 0. Pins that match the pattern “XYZ/D” are now members of both SG1 and SG2. However,
they are only active sinks in SG2, which is the highest ranked parent skew group so far. Pins that do not match this pattern remain
active sinks in SG1.
The third command defines another exclusive skew group SG3. Exclusive sinks are specified so this skew group has a rank of 2,
which is one higher than the current highest rank of 1. Pins that match the pattern “XYZ_01/D” are now members of skew groups
SG1, SG2, and SG3. However such pins are only active sinks in SG3, which is the highest ranked parent skew group. Pins that
matched the pattern “XYZ/D” but not “XYZ_01/D” are members of both SG1 and SG2 but only active sinks of SG2. Sinks that do
not match the pattern XYZ/D are active sinks in SG1.
The rank of a skew group can be accessed via the exclusive_sinks_rank property.
Finding Active Skew Group Sinks
Use the following command to find all the sink members of a skew group:
get_ccopt_property –skew_group name sinks
Use the following command to find all the active sink members of a skew group:
get_ccopt_property –skew_group name sinks_active
Use the following command to find all the skew groups for which a pin is a sink member:
get_ccopt_property –pin name skew_groups_sink
Use the following command to find all the skew groups for which the pin is an active sink:
get_ccopt_property –pin name skew_groups_active_sink
Use the following command to find all the skew groups which are active at a pin, either passing through the pin or for which the pin is
an active sink:
get_ccopt_property –pin name skew_groups_active
Note : In debugging CCOpt-CTS skew or CCOpt initial balancing, the ‘active’ properties above should be used, since these reflect
the constraints CTS will respect. For example, if a pin is configured as a sink of skew group but the skew group does not propagate
to the pin due to a lack of connectivity, the pin will not be an active sink of the skew group. After defining skew groups or modifying
existing skew groups it is recommended to invoke the report_ccopt_skew_groups or ccopt_design command to ensure that the
CTS timer is updated before checking the active sinks properties.
Modifying Skew Groups
The modify_ccopt_skew_group command is used to make changes to the sink and ignore pins associated with a skew group. The
syntax of the command is provided below.
modify_ccopt_skew_group
[-help]
[-make_exclusive]
-skew_group skew_group_name
[-add_sinks pins | -remove_sinks pins]
[-add_ignore_pins pins | -remove_ignore_pins pins]
The -add_sinks and -remove_sinks parameters are used to add and remove sinks. The -add_ignore_pins and -
remove_ignore_pins parameters are used to add and remove ignore pins, and are discussed below.
The set_ccopt_property command can be used to modify properties of a skew group, including
the target_insertion_delay, target_skew, and constrains properties.
Skew Group Ignore Pins
Specifying a pin as an ignore pin of a skew group stops CTS from considering the latency to that pin in that specific skew group, and
stops that specific skew group propagating through and beyond that pin. Other skew groups at the pin are not affected. Skew group
ignore pins are always applicable regardless of the skew group rank.
For example, if a leaf flip-flop clock pin is specified as a skew group ignore pin, CTS will not balance that flip-flop with other sinks for
the same skew group. Balancing of other skew groups, possibly involving the same pins, would not be affected.
If a non-leaf pin is specified as a skew group ignore pin, for example a multiplexer input, CTS will ignore both the latency to and
through that multiplexer input in the given skew group. Other skew groups passing through the same multiplexer input would not be
affected. In such an example, any flip-flops in the fanout of the multiplexer would cease to be active sinks of the skew group.
Deleting the Clock Tree Specification
The delete_ccopt_clock_tree_spec command can be used to remove all skew groups, clock trees, and associated data. However,
this command does not reset property settings on pins, instances and other database entities. The reset_ccopt_config command
can be used to remove both the clock tree specification and all CCOpt property settings.
