reset
*System reset
A system reset is generated when any of the following events occur:
1. Low level on NRST pin (external reset)
2. Window watchdog count termination (WWDG reset)
3. Independent watchdog count termination (IWDG reset)
4. Software reset (SW reset)
5. Low power management reset
* Power reset
A power reset is generated when one of the following events occurs
1. Power-on/power-down reset (POR/PDR reset)
2. Return from standby mode
* Backup area reset
The backup area has two dedicated resets, they only affect the backup area
A backup area reset occurs when one of the following events occurs
1. Software reset, backup area reset can be generated by setting the BDRST bit in the backup area control register (RCC_BDCR)
2. On the premise that both VDD and VBAT are powered off, powering on VDD or VBAT will cause the backup area to reset.
clock control
*What is a clock?
When the clock is turned on, the corresponding equipment will work.
* clock source
Three different clock sources can be used to drive the system clock (SYSCLK)
1. HSI oscillator clock (high speed internal clock)
2. HSE oscillator clock (high speed external clock)
3. PLL clock (phase-locked loop multiplier clock)
Secondary clock source:
1. 40kHz low-speed internal RC (LSIRC) oscillator
2. 32.768kHz low-speed external crystal (LSE crystal)
For example, we can set the HSE oscillator clock in CubeMX.
Then configure the Clock
