SOC Architecture
Before we start, let's first look at what is clock gating technology. As the name implies, it uses logic gate technology to control the on-off of the clock .
So why do you need to control the on and off of the clock? Mainly based on the following reasons.
First of all, with the development of the process and the increase of the design scale, the power consumption generated by the clock tree accounts for a higher and higher proportion of the entire SoC power consumption, sometimes almost accounting for about 50%.
Regarding the clock tree, the students at the front end may not be familiar with it. To put it simply, the clock of the SoC is generally output by the reference clock through the PLL and the digital frequency divider, and it may be connected to drive thousands of register clock terminals later .
At this time, it is impossible for any single cell to have such a large driving capacity, so a large number of buffers need to be inserted, and in order to ensure the same delay to each register, the clock tree needs to be balanced . The entire clock tree probably grows like the following figure,
- The first level buffer is called root,
- The buffer in the middle is called branch,
- The last level of buffer is called leaf (the name of the technology is so simple, rough, and easy to understand the picture):
If the PLL still has a clock output when our chip is not working, the entire clock tree will still generate a lot of power consumption.
Next, let's take a look at the structure diagram of the edge trigger. From the figure, we can see that even if the D terminal remains unchanged, the change of the clock terminal will consume some energy. Students who want to study in depth can derive it by themselves (you can ignore the two reset signals