table of Contents
4.1 Overview of Computer Storage System
4.1.1 Features of the storage system
4.3.3.3 set-associative mapping
4.1 Overview of Computer Storage System
4.1.1 Features of the storage system
1. The storage location means that the storage is inside or outside the computer. Internal memory usually refers to main memory. The processor has its own local memory, which exists in the form of registers. Cache is another form of memory storage.
2. Three concepts related to internal memory:
①Word: "natural unit" of memory organization. The word length is usually equal to the number of data bits and instruction length of an integer.
②Addressable unit: In some systems, the addressable unit is a word. In any case, the relationship between the length of the address A and N is the number of addressable units: 
.
③Transmission unit: For the main memory, this refers to the number of bits that are read or written into the memory each time.
3. Another difference between different types of memory is the different access methods of data units. The access methods include the following four categories:
- Sequential storage: The memory is organized into many data units called records, which are accessed in a specific linear sequence. The stored address information is used to separate records and help index. For example, the tape drive uses sequential access.
- Direct access: A single block or a unique address based on the physical storage location is recorded. By using direct access to reach the required block, and then sequentially search, count or wait in the block, and finally reach the required position. For example, the disk drive system uses a direct access method.
- Random access: Each addressable storage location in the memory has a unique physical orchestration addressing mechanism. The time to access a given storage location is fixed and does not depend on the sequence of previous accesses. Therefore, any storage location can be randomly selected, directly addressed and accessed. For example, the main memory and some high-speed cache systems use random access methods.
- Associated access: random access memory, which allows checking and comparing certain specified bits in a word to see if they match a specific pattern, and it can be performed in all words at the same time. Therefore, a word is retrieved by its content rather than its address. For example, the cache uses an associated access method.
4. Three performance parameters of memory
①Access time (delay): For random access memory, this is the time to perform a read or write operation. For non-random access memory, this is the time it takes to locate the read-write structure to the desired storage location.
②Storage cycle time: Mainly used for random access memory, it is access time + additional time required before the next access starts. Related to the system bus.
③Transmission rate: the rate at which data is transferred in or out of the storage unit. For random access memory, it is equal to "1/cycle time". For non-random access memory, there are the following relationships:
4.1.2 Memory hierarchy
As the level drops, the price per bit↓, the capacity↑, the access time↑, and the frequency of the processor accessing the memory↓.
4.2 Cache memory principle
1. The purpose of the cache memory is to make the memory speed close to the fastest available memory speed, while providing a large memory capacity at the price of a cheaper semiconductor memory.
2. Cache/main memory structure
3. Cache read operation: When the cache hits, the data and address buffer are useless, communication is only carried out between the processor and the cache, and there is no signal transmission on the system bus at this time. When the cache misses, the required address is loaded on the system bus, and the data is submitted to the cache and CPU through the data buffer.
4.3 Design elements of cache
4.3.1 Mapping function
There are usually three mapping methods:
4.3.1.1 direct mapping
Direct mapping is the simplest mapping technique, which maps each block in main memory to a fixed available cache line.
The direct mapping can be expressed as: i = j mod m
Among them, i = cahe line number j = block number of main memory m = cache line number
Each block in the main memory is mapped to a unique row in the cache, and then the next m blocks are mapped to the corresponding position in the cache in turn.
The basic mapping mechanism of direct mapping is as follows:
In order to access the cache, each main memory address can be seen as composed of three domains. The lowest w bit identifies a unique word or byte in a block, and the remaining s bit specifies one of the 2^s blocks of main memory. The cache logic converts the s bit into a tag field of the sr bit (the most significant part) and a row field of r bits . The latter identifies one of m = 2'cache lines.
- Address length = (s + w) bits
- Number of addressable units = 2 ^ (s + w) words or bytes
- Block size = row size = 2^w words or bytes
- Number of blocks in main memory = 2 ^ (s + w) / 2 ^ w = 2 ^ s
- The number of rows in the cache = m = 2 ^ r
- Cache capacity = 2 ^ (r + w) words or bytes
- Mark length = (s-r) bits in order to distinguish it from other blocks loaded into this line
4.3.3.2 Associative mapping
Allow each block of main memory to be loaded into any row in the cache.
In this case, the cache control logic simply expresses the storage address as a tag field plus a word field. The tag field is used to uniquely identify a main memory block. In order to determine whether a block is in the cache, the cache control logic must simultaneously check the tags in each row to see if they match.
The basic mapping mechanism of fully associative mapping is as follows:
- Address length = (s + w) bits
- Number of addressable units = 2 ^ (s + w) words or bytes
- Block size = row size = 2^w words or bytes
- Number of blocks in main memory = 2 ^ (s + w) / 2 ^ w = 2 ^ s
- The number of cache lines = not determined by the address format
- Mark length = s bits
4.3.3.3 set-associative mapping
Combining the advantages of direct mapping and fully associative mapping
In the group associative mapping, the cache is divided into v groups, each group contains k rows, and their relationship is: m = v * k i = j mod v
Among them, i = cache group number j = main memory block number m = number of cache rows v = number of groups k = number of rows in each group
This is called k-way group associative mapping. The group associative map cache is physically a cache that uses v fully associative maps. At the same time, it can also be regarded as the simultaneous use of k directly mapped caches. Each cache directly mapped is called a way and includes v cache lines.
The basic mapping mechanism of group associative mapping is as follows:
- Address length = (s + w) bits
- Number of addressable units = 2 ^ (s + w) words or bytes
- Block size = row size = 2^w words or bytes
- Number of blocks in main memory = 2 ^ (s + w) / 2 ^ w = 2 ^ s
- The number of rows in each group in the cache = k
- Number of groups = v = 2 ^ d
- Number of cache rows = m = kv = k * 2 ^ d
- Cache capacity = k * 2 ^ d words or bytes
- Mark length = (s-d) bits
4.3.2 Replacement algorithm
- LRU: Replace the blocks that have not been accessed for the longest time in the cache
- FIFO: replace those blocks that have been in the cache for the longest time
- LFU: Replace the least accessed block in the cache
- The technology is not based on usage, it is arbitrarily selected among the candidate rows and then replaced.