Principles of Computer Chapter storage system (1)

4.1 storage system hierarchy

1. Basic storage system

1. The input device program and data into the main memory;
2. CPU instruction fetch;
3. CPU read data during execution of instructions;
4. CPU write-back operation results;
5. Result output device;

2. Causes slow main memory

• Main memory growth are not synchronized with the CPU;
• Multiple access memory during execution of instructions;
  

3. The main causes of insufficient memory capacity

• Technical factors there are restrictions determined by the capacity of the motherboard CPU, motherboard and other indicators related art
  
• Main memory applications continues to expand
  

4. The hierarchical structure of the storage hierarchy

• L1 Cache integrated in the CPU, sub-data Cache (D-Cache) and instructions Cache (I-Cache)
• Early in L2 Cache CPU on the motherboard or integrated with the same circuit board. With the improvement of L2 Cache process is integrated in the CPU core, regardless of the D-Cache, and I-Cache

Harvard architecture (Harvard architecture)

• A memory structure storing instructions and data are stored separately, and may support: storing data and instructions in parallel, the instruction is expected to improve the efficiency of the processor; Further, instructions and data may have different data widths, such as Microchip's PIC16 chip program instructions is 14 bits wide but the data is 8 bits wide.
• Harvard architecture currently in use: PIC series, Motorola's MC68 series, Zilog's Z8 series, ATMEL's AVR series and ARM's ARM9, ARM10 and ARM11.

The theoretical basis of the hierarchical structure of the storage system 5

Principle of locality

Temporal locality

• Information is now accessed 2 will be accessed again in the near future
• The program structure reflects the temporal locality: loop structure

Spatial locality

• 2 now access information, the next time access to the information in the vicinity of 2
• Program structure embodied spatial locality: Sequence structure

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4.2 Data organization of main memory

1. storage word

• The number of bits of a memory cell contained in main memory;
• Currently most of the main computer memory byte addressed memory word length is also increasing, such as a 16-bit word length, 32-bit word length and 64 bit word length;

2. The relationship between data storage and boundaries

1. By storing data boundary alignment
   
2. Boundary alignment data storage fails
   
3. Boundary alignment relationship with the memory address (in Example 32)
   

• Start address of the double word boundary alignment data 000 is the last three (integer multiple of 8 bytes);
• The end of a long list of start addresses aligned two boundary 00 (an integral multiple of 4 bytes);
• Half-length of the boundary alignment of the start address of the last bit is 0 (an integer multiple of 2 bytes)

3. The big-endian and little-endian storage

Detailed big-endian and little-endian mode

• Big-endian: the highest byte address (MSB) address of the data
  that is corresponding to the high byte of the low address, high address low byte corresponds
• Little-endian: the lowest address byte (LSB) address of the data
  that is corresponding to the low byte of the low address, high address high byte corresponds
  
  example: 0x12 34 56 78 Digital stored in the memory

大端模式下：
低地址----------->高地址
0x12 | 0x34 | 0x56 | 0x78
小端模式下：
低地址----------->高地址
0x78 | 0x56 | 0x34 | 0x12

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4.3 static memory works

1.SRAM memory cell structure

2.SRAM storage unit works

Write process

read process

remain

3. The structure of SRAM

Static memory is divided into a single coding structure and the double structure of the decoder


6116 static memory structure

2114 static memory structure

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4.4 Dynamic Memory works

1.SRAM insufficient storage unit

The basic structure of the memory cell 2.DRAM

Works 3.DRAM storage unit

Refresh 4.DRAM storage unit

• Refresh cycle: time interval between two refreshes;
• DRAM refresh double structure for decoding rows, need to know the number of rows RDAM chip memory matrix;
• Refresh address given by the refresh address counter

5.DRAM contrast to the SRAM

6. Other configuration of DRAM memory cells

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4.5 Storage Expansion

Basic concepts and types of storage expansion

Comprising storage expansion bit extension, extension word, word bit extension, regardless of the type of storage expansion must be completed between the CPU and main memory address lines, data lines, cable control

Example 2 bit extension

Example 3. Extended Word

4. word bits while extending