The level and structure of memory
Classify the different angles from the memory:
1. Press role in the computer (hierarchical) classification
(1) a main memory. Referred to as the main memory, also known as the memory (RAM), for storing a large number of programs and data required during the operation of the computer, the CPU can directly be accessed randomly, and may also tell the buffer memory (Cache) and a secondary memory for exchanging data , which is characterized by a smaller capacity, faster access, higher unit price.
(2) a secondary memory. Referred to as secondary memory, also known as the external memory (external memory), main memory is a backup memory used to store the current program and the temporarily unused data, and some require permanent stored information, it can not directly exchange information with the CPU. Which is characterized by a great capacity, the access speed is slow, low unit cost.
(3) a cache memory. Acronym Cache, located between the main memory and the CPU, for storing data and program segment being executed, so that the CPU can use them at high speed. Cache access speed can be matched to the speed of the CPU, but a small storage capacity and high prices. The current high-end computer they are usually made in the CPU.
2. Press the storage media classification
According to the storage medium, the memory can be divided into a magnetic surface of the memory (disk, tape), magnetic core memory, a semiconductor memory (MOS type memory, a bipolar memory), and optical storage (CD-ROM).
3. According to the way classification
(1) Random Access Memory (RAM). Any memory cell can be a random access memory, and the access time is independent of the physical location of the memory cell. The advantage is easy to read, flexible, mainly used as a main memory or a cache memory. RAM is divided into a static RAM (to trigger the principle of registration information, SRAM) and dynamic RAM (to charge the capacitor the principle of registration information, DRAM).
(2) a read only memory (ROM). The contents of the memory can not be written and read randomly. Once the information is written to the memory on fixed, even if the power outage, the contents will not be lost. Thus, it is usually stored fixed program, constants and character font, and even the operating system for curing. It may be random access memory with the main memory as part of a common, unified address field constituting the main memory.
Derived from the ROM memory also contains a rewritable type can be repeated, ROM and RAM access are a random access manner . Read-only memory in the broad sense may have been by electrically erasable writing, etc., the concept of which is "read-only" no reservations, but still retains the content retaining off, random reading characteristics, but the write speed ratio read speed is much slower.
(3) serial access memory. When the memory cell read / write operation, the physical address of the basis having the addressing sequence, including sequential access storage (e.g., a magnetic tape, the SAM) with direct access storage (such as disk, DAM).
SUMMARY sequential access memory can access in a certain order, the length of the access time on the physical location of information about the bank, which is characterized by a slow access speed. Random access memory as neither directly access any one memory cell as RAM, but not as full sequential access memory in order to access, but somewhere in between. When access to information is typically looking for a small area (e.g., a track on the disk) in the entire memory, and then the order to find in a small area.
4. Information Classification preservability
After a power failure, information stored in a memory called the disappearance volatile memory, such as RAM. After a power failure, information is referred to as memory information remains a nonvolatile memory, such as ROM, magnetic storage, and optical storage surface. If the information stored in a storage unit is read out, the original information is stored is destroyed, it is called destructive readout; if read, the reading unit is stored information is not destroyed, called non-destructive readout , a memory having destructive readout, after each readout operation, a regeneration operation must immediately to recover the information is destroyed. .
The memory has three key performance indicators, i.e. the storage capacity, speed, and storage costs per unit. These three indicators mutual restraint, memory system design goal is high-capacity, low cost and high speed.
(1) Storage Capacity * = word length of words stored (e.g. 1M * 8 bits). Storage size of the memory word represents the address space, the amount of data word length of one access operation.
(2) Unit Cost: Total Cost = Price per / total capacity.
(3) storage speed: width = data rate / data memory cycles.
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- Access time ( T A ): Access time is the time from the start a memory operation to complete the operation experienced, time is divided into read and write times .
- Access period ( T m ): access cycle or period known as read-write access cycle. It refers to the total time required to complete a memory read and write operations, i.e., the minimum time required between (a read or write operation) continuous two independent memory access operation interval .
- Main memory bandwidth ( B m ): also known as main memory bandwidth, data transfer rate, the main memory from the second represents the maximum amount of information out of units of characters / second, bytes / second (B / s) or bits / second (b / s).
It is not equal to the stored access time period, typically greater than the stored memory cycle time. This is because any kind of memory, after the read and write operations, there must be a period of recovery time to restore internal state. For destructive readout of a memory access cycle is often much greater than the access time, because of the need for regeneration immediately after the read out information in the memory.
An operating system stored on the hard disk, you first need to be conducted to the main memory, the boot program is usually stored in ROM, read and write operations need to be running, so should be used RAM.
The hierarchical structure of the memory
In order to solve large-capacity storage system, high speed and low cost constraints of three mutually contradictory, in a computer system, typically a multi-level memory structure, as shown in FIG. In the drawing from top to bottom, lower and lower price, more slowly, increasing capacity, frequency of the CPU has access getting low.
In fact, the storage system hierarchy is mainly reflected in the "Cache - Main Memory" level and the "main memory - secondary storage" level. The former problem CPU and main memory speed mismatch, the latter to solve the problem of the storage capacity of the system. In the storage system, the Cache, main memory can directly exchange information with the CPU, and secondary memory will have to exchange information via the main CPU memory; CPU and main memory, the Cache, auxiliary storage can exchange information.
Hierarchy tertiary storage system and its components
Mobilization of data between the main memory and the Cache is done automatically by the hardware, all are transparent to the programmer; the data mobility between the main memory and secondary memory is hardware and operating system together to complete, the application member is transparent .
In the "main memory - Cache" and "main memory - auxiliary storage" level, the upper layer of the content is just under one copy of the content, ie Cache (main memory) the contents of the main memory only (auxiliary storage) part of the content.
The semiconductor random access memory
74138 decoder strobe terminals G1 is high, the other two is low, the address before the end of the translated binary coded at a low level at a respective output terminal.
SRAM works
Memory element static random access memory (SRAM) is a flip-flop (six MOS) information to the memory, therefore even after the information is read, it keeps its original state without the need for regeneration (nondestructive readout ). However, as long as the power is turned off, the stored original information are lost, so it belongs to a volatile semiconductor memory. SRAM access speed, but a low degree of integration, power consumption is large, a buffer memory is generally used to tell the composition.
DRAM works
Dynamic random access memory (DRAM) charge on the gate is the use of capacitive storage circuits to store meta information common basic DRAM memory circuits are generally divided into three and single tube. Using DRAM address multiplexing, the address lines are 1/2 of the original, and the branch address signals, column two transmissions . For respect SRAM, DRAM having easy integration, low price, low capacity and power consumption advantages, but the access speed of the DRAM is slower than SRAM, typically used to form a large capacity main memory systems.
DRAM saved information will automatically disappear (volatile memory), for which must be refreshed from time to time, usually takes 2ms, this time called the refresh cycle. Commonly used methods are three kinds refresh: refresh centralized, decentralized and asynchronous refresh refresh.
(1) centralized Refresh: means in a refresh cycle by a fixed period of time, sequentially line memory one by one all the regeneration, during read and write operations to the memory is stopped, is called "dead time", also known as the access keep the "dead zone." The advantage is not concentrated refresh operation when the refresh affect read and write operations, a higher access speed of the system; disadvantage is concentrated during refresh (dead zone) can not access the memory.
（2）分散刷新：把对每行的刷新分散到各个工作周期中。这样，一个存储器的系统工作周期分为两部分：前半部分用于正常读、写或保持；后半部分用于刷新某一行。这种刷新方式增加了系统的存取周期，如存储芯片的存取周期为 0.5μs，则系统的存取周期为 1μs。分散刷新的优点是没有死区；缺点是加长了系统的存取周期，降低了整机的速度。
（3）异步刷新：异步刷新是前两种方法的结合，它既可以缩短“死时间”，又能充分利用最大刷新间隔为 2ms 的特点。具体做法是将刷新周期除以行数，得到两次刷新操作的时间间隔 t，利用逻辑电路每隔时间 t 产生一次刷新请求。这样可以避免使 CPU 连续等待过长的时间，而且减少了刷新次数，从根本上提高了整机速度。
DRAM 的刷新需注意以下问题：（1）刷新对 CPU 是透明的，即刷新不依赖外部的访问；（2）动态 RAM 的刷新单位是行，故刷新操作时仅需要行地址；（3）刷新操作类似于读操作，但又有所不同。刷新操作仅给栅极电容补充电荷，不需要信息输出。另外，刷新时不需要选片，即整个存储器中的所有芯片同时被刷新。
SRAM 和 DRAM 都满足断电内容消失，但需要刷新的只有 DRAM，而 SRAM 不需要刷新。
| 特点 \ 类型 | SRAM | DRAM |
| 存储信息 | 触发器 | 电容 |
| 破坏性读出 | 非 | 是 |
| 需要刷新 | 不要 | 需要 |
| 送行列地址 | 同时送 | 分两次送 |
| 运行速度 | 快 | 慢 |
| 集成度 | 低 | 高 |
| 发热量（功耗） | 大 | 小 |
| 存储成本 | 高 | 低 |
| 主要用途 | 高速缓存 | 主机内存 |
ROM 器件有两个显著的优点：
（1）结构简单，所以位密度比可读写存储器高。
（2）具有非易失性，所以可靠性高。
根据制造工艺不同，ROM 可分为掩膜式只读存储器（MROM）、一次可编程只读存储器（PROM）、可擦除可编程只读存储器（EPROM）、闪速存储器（Flash Memory）和固态硬盘（Solid State Drives）。
MROM 写入后任何人无法改变其内容。PROM 允许用户利用专门的设备（编程器）写入自己的程序，一旦写入，内容就无法改变。EPROM不仅可以由用户利用编程器写入信息，而且可以对其内容进行多次改写。需要修改 EPROM 内容时，先将其全部内容擦除，然后编程。
主存容量的扩展：位扩展法，字扩展法，字位同时扩展法。
双端口 RAM 和多模块存储器
双端口 RAM 是指同一个存储器有左、右两个独立的端口，分别具有两组相互独立的地址线、数据线和控制线，允许两个独立的控制器同时异步地访问存储单元。当两个端口的地址不相同时，在两个端口上进行读写操作一定不会发生冲突。
两个端口同时存取存储器地同一地址单元时，会因数据冲突造成数据存储或读取错误。两个端口对同一主存操作有以下4 种情况：
- 两个端口不同时对同一地址单元存取数据。
- 两个端口同时对同一地址单元读出数据。
- 两个端口同时对同一地址单元写入数据。
- 两个端口同时对同一地址单元操作，一个写入数据，另一个读出数据。
其中，第 1 种和第 2 种情况不会出现错误；第 3 种情况会出现写入错误；第 4 种情况会出现读出错误。
为提高访存速度，常采用多模块存储器，常用的有单体多字存储器和多体低位交叉存储器。
1.单体多字存储器
单体多字系统的特点是存储器中只有一个存储体，每个存储单元存储 m 个字，总线宽度也为 m 个字。一次并行读出 m 个字，地址必须顺序排列并处于同一存储单元。
单体多字系统在一个存取周期内，从同一地址取出 m 条指令，然后将指令逐条送至 CPU 执行，每隔 1/m 存取周期，CPU 向主存取一条指令。这增大了存储器的带宽，提高了单体存储器的工作速度。
缺点：指令和数据在主存内必须是连续存放的，一旦遇到转移指令，或操作数不能连续存放，这种方法的效果就不明显。
2.多体并行存储器
多体并行存储器由多体模块组成。每个模块都有相同的容量和存取速度，各模块都有独立的读写控制电路、地址寄存器和数据寄存器，它们既能并行工作，又能交互工作。多体并行存储器分为高位交叉编址（顺序方式）和低位交叉编址（交叉方式）两种。
（1）高位交叉编址：高位地址表示体号，低位地址为体内地址。采用高位交叉编址方式的存储器仍是顺序存储器。
（2）低位交叉编址：低位地址为体号，高位地址为体内地址。由于程序连续存放在相邻体中，因此采用此编址方式的存储器称为交叉存储器。
多体模块结构的存储器采用低位交叉编址后，可在不改变每个模块存取周期的前提下，采用流水线的方式并行存取，提高存储器的带宽。
高速缓冲存储器
高速缓冲技术是利用程序访问的局部性原理，把程序中正在使用的部分存放在一个高速的、容量较小的Cache中。使 CPU 的访存操作大多数针对 Cache 进行，从而大大提高程序的执行速度。
Cache 位于存储器层次结构的顶层，通常由 SRAM 构成。
CPU 与 Cache 之间的数据交换以字为单位，而 Cache 与主存之间的数据交换则以 Cache 块为单位。
在Cache 中，地址映射是指把主存地址空间映射到 Cache 地址空间，即把存放在主存中的程序按照某种规则装入Cache。地址映射不同于地址变换。地址变换是指 CPU 在访存时，将主存地址按映射规律换算成 Cache 地址的过程。地址映射的方式有以下 3 种。
1.直接映射
主存数据块只能装入 Cache 中唯一的位置。若这个位置已有内容，则产生块冲突，原来的块将无条件地被替换出去（无须使用替换算法）。直接映射的块冲突概率最高，空间利用率低。直接映射的关系可定义为 j = i mod 2c
直接映射的地址结构为
| 主存字块标记 | Cache 字块地址 | 字块内地址 |
2.全相联映射
可以把主存数据块装入 Cache 中的任何位置。
全相联映射的地址结构为
| 主存字块标记 | 字块内地址 |
3.组相联映射
将 Cache 空间分成大小相同的组，主存的一个数据块可以装入一组内的任何一个位置，即组间采取直接映射，而组内采取全相联映射。两个 Cache 块为一组即二路组相联。
组相联映射的地址结构为
| 主存字块标记 | 组地址 | 字块内地址 |
Cache 总容量包括：存储容量、标记列阵容量（有效位、标记位、一致性维护位、替换算法控制位）。
每个 Cache 行对应一个标记项（有效位、标记位……）
Cache 中主存块常用的替换算法有随机（RAND）算法、先进先出（FIFO）算法、近期最少使用（LRU）算法和最不经常使用（LFU）算法。与操作系统算法类似，不再赘述。
Cache 中的内容是主存块的副本，当对 Cache 中的内容进行更新时，就需选用写操作策略，使 Cache 内容和主存内容保持一致。此时分两种情况：
对于 Cache 写命中（write hit），有两种处理方法。
（1）全写法（写直通法、write - through）。当 CPU 对 Cache 写命中时，必须把数据同时写入 Cache 和主存。
（2）写回法（write - back）。当 CPU 对 Cache 写命中时，只修改 Cache 的内容，而不立即写入主存，只有当此块被换出时才写回主存。这种方法减少了访存次数，但存在不一致的隐患。采用这种策略时，每个 Cache 行必须设置一个标志位（脏位），以反应此块是否被修改过。
对于 Cache 不命中，也有两种处理方法
（1）写分配法（write - allocate）。加载主存中的块到 Cache 中，然后更新这个 Cache 块。它试图利用程序的空间局部性，但缺点是每次不命中都需要从主存中读取一块。
（2）非写分配法（not - write - allocate）。只写入主存，不进行调块。
Cache的写命中和写未命中，就是磁盘或者内存上的存储区域之前有没有写过数据。如果有，这次再写到相同的区域叫写命中；如果写到其他区域，叫写未命中。
非写分配法常与全写法合用，写分配法通常和写回法合用。
对于由高速缓存、主存、硬盘构成的三级存储体系，CPU 访问该存储系统时发送的地址为主存物理地址。当 CPU 访存时，先要到 Cache 中查看该主存地址是否在 Cache 中，所以发送的是主存物理地址。只有在虚拟存储器中，CPU 发出的才是虚拟地址。磁盘地址是外存地址，外存中的程序由操作系统调入主存中，然后在主存中执行，因此 CPU 不可能直接访问磁盘。
采用 指令Cache 和 数据Cache 分离的主要目的是减少指令流水线的资源冲突。
局部性原理的基本含义是：在程序执行过程中，程序对主存的访问是不均匀的（即局部）。
页式虚拟存储方式和段页式都以页为单位和主存交互。
虚存对应用程序员透明，对系统程序员不透明。
在虚拟存储器中，当程序正在执行时，由操作系统完成地址映射。
若 Cache 行长太大，Cache 项数变少，因而命中的可能性减小。