Principles of Computer Composition and structure of the schema (Chapter III CPU subsystem)
1, the operation member
✔ 3-39
- M: storage means (a storage unit in the storage section)
- R: general register group
- ALU: arithmetic logic means
Task: an input / direct delivery, processing, output
Operator configured
- Input logic (select or register)
- Arithmetic and logic operation means
- Output logic (direct-shift, byte swapping)
2, the control section
Figure 3-43 ✔P137 system bus (address bus, data bus + + Control Bus)
Programmable control means
1) a general register Ri, i programmable
2) the program counter PC, use: instruction command is stored in a memory location
After taking site, PC content increase (programmable)
3) Program status register PSW, there are two seats (programmable)
4) SP, and leaves the R similar manner was separated out because of their special alone
PC>PSW>SP>Ri
Non-programmable control means
1) IR standing instruction storage
2) registers, C and D are not programmable
3) Address Register MAR-> address bus
4) the data register MDR <-> data bus
P3, instruction
1) General instruction format
2) common addressing mode
3) for a user instruction type
Instruction format
1. Basic operation code format op_ θ, A_ address code D
This instruction opcode decide what to do
2. The four-address operand address of D1, D2 operand address, D3 result address, instruction address (PC may be substituted) under D4
3. The three / two / one address structure (1) itself less operand (2) abbreviated operands
4. The zero address or special instructions for stack operations
Instruction word length
1) address structure:
Significant address structure
Implicit address structure - generally refers to the zero address structure
2) the instruction address provided
(1) memory cell address code
(2) the register number