Principles of Computer Composition (Third Edition) Tang Shuofei - Chapter 8 Structure and Function of CPU - Exercises after class

chapter eight

8.1 What are the functions of the CPU? Draw its structural block diagram and briefly explain the function of each component.

answer:
CPU function: The CPU has the functions of controlling the sequential execution of the program, generating the control commands required to complete each instruction, controlling the time of various operations, performing arithmetic and logic operations on data, and processing interrupts. Its block diagram is as follows.

The registers in the figure include special-purpose registers (such as program counter, instruction register, stack indicator, memory address register, memory data register, status register, etc.) and general-purpose registers (store operands); CU generates various micro-operation command sequences; ALU
completes Arithmetic and logical operations; the interrupt system is used to handle various interrupts.

8.2 What is an instruction cycle? Is there a fixed value for the instruction cycle? Why?

answer:
instruction cycleIt is the total time required by the CPU to fetch and execute an instruction, that is, the time for the CPU to complete an instruction. Since the operation functions of various instructions are different, the instruction cycle of various instructions isdifferentYes, the length of the instruction cycle is mainly related to the number of memory accesses of the instruction in the execution phase and the operations that need to be completed in the execution phase.

8.3 Draw the flow chart of the instruction cycle, and explain the function of each sub-cycle in the figure.

Answer:
The flow chart of the instruction cycle is shown in the figure below. The fetch cycle completes the operations of fetching instructions and analyzing instructions; the indirect cycle is used to fetch the effective address of the operand; the execution cycle completes the operation of executing instructions; the interrupt cycle is when the CPU When responding to an interrupt, the operation of protecting the program breakpoint, closing the interrupt by hardware, and sending the vector address to the PC (hardware vector method) is completed by the interrupt implicit instruction.

8.4 Suppose there are these components in the CPU: PC, IR, SP, AC, MAR, MDR and CU.

(1) Draw the data flow (starting from the instruction fetch) of the data fetch instruction "LDA@X" (fetching the content of a certain address unit in the main memory to AC) that completes indirect addressing.
(2) Draw the data flow of the interrupt cycle.
Answer:
The data flow direction in the CPU is related to the data path structure adopted, and the data flow in different data paths is different. Commonly used data path structure methods include direct connection, single bus, double bus, and triple bus. At present, most of them use bus structure, and the direct connection method is only suitable for machines with particularly simple structures.
For the sake of simplicity, this question uses a single-bus structure to connect the components given in the question. The block diagram is as follows:

(1) LDA@X instruction cycle data flow chart:

(2) The interrupt cycle flow chart is as follows:

8.5 What is the stage before the interrupt cycle? What is the stage after the interrupt cycle? What should the CPU do during the interrupt cycle?

Answer:
Before the CPU interrupt cycle isexecution cycle, after the interruption cycle isfetch cycle.
A complete instruction cycle should includeFetch, Indirect, Execute and Interrupt4 subcycles.
The CPU completes the following operations in the interrupt cycle: CPU memory access operation; save program breakpoint; hardware interrupt; send the vector address to the program counter (hardware vector method) or send the interrupt identification program entry address to the program counter (software query method).

8.6 There are several data types in the memory: instruction code, operation data, stack data, character code and BCD code, how does the computer recognize these codes?

Answer:
The information fetched by the CPU from the memory during the instruction fetch phase isinstruction code.
What the CPU fetches from memory during the execution phase can beOperation data, character code or BCD code, specifically which information is related toinstruction opcoderelated.
The data obtained when accessing memory according to the address indicated by the stack pointer SP isstack data。

8.7 What is system parallelism? What is the difference between coarse-grained parallelism and fine-grained parallelism?

Answer:
The so-called parallel inclusionSimultaneity and ConcurrencyTwo ways. The former means that two or more events occur at the same time, and the latter means that two or more events occur at the same time. That is to say, if two or more functions of the same or different nature are completed at the same moment or within the same period of time, as long as they overlap each other in time, there is parallelism.
Parallelism can be divided into coarse-grained parallelism and fine-grained parallelism.
coarse-grained parallelismIt is to run multiple processes on multiple processors separately, and the multiple processors cooperate to complete a program, which is generally realized by algorithms (software).
fine-grained parallelismIt refers to the parallelism at the operation level and instruction level of the processor, which is generally realized by hardware, and instruction pipelining is an important technology.

8.8 What is instruction pipeline? Draw a schematic diagram of instruction two-level pipeline and four-level pipeline, which one of them can improve the processor speed more, and why?

answer:
instruction pipelineIt is to change the rules of serial execution of each instruction in order, so that the machine will fetch the next instruction while executing the previous instruction. The following figures (a) and (b) are the schematic diagrams of the second-level pipeline and the fourth-level pipeline of the instruction respectively.

Divide the instruction cycle more finely, so that more instructions can be executed at the same time, which can improve the processor speed, so the processing speed of the four-stage pipeline is higher than that of the two-stage pipeline.

8.9 When encountering what situation will the pipeline be blocked? Give an example.

Answer:
There are generally three situations where the pipeline is blocked:
(1) During the overlapping execution of instructions, the hardware resources cannot meet the requirements for overlapping execution of instructions, and resource conflicts occur. If at the same time, several overlapping instructions need to fetch instructions, fetch operands, and store results, all need to access memory, and memory access conflicts will occur.
(2) There is a certain relationship between adjacent instructions of the program. For example, when an instruction needs to use the execution result of the previous instruction, and these instructions are overlapped and executed in the pipeline, data correlation may be caused.
(3) When the pipeline encounters a branch instruction, if an instruction has to wait for the previous (or several) instructions to make a decision on the transfer direction before entering the pipeline, control correlation occurs.

8.10 illustrates several data correlations in the pipeline with examples.

Answer:
There are three types of data correlation in the pipeline:
(1)Read after write (RAW).
As in the following set of instructions, $I_1$The operation result of the instruction should be written into R 1 R_1 first$R_1$,After that $I_2$Instruction read $R_2$The content, that is, the write command is in the front, and the read command is in the back.
$$\begin{gathered} I_{1}ADD{R}_1,R_2,R_3；(R_2)+(R_3)\to R_1 \\ {I}_{2}SUB{R}_4,R_1,R_5；\left(R_1\right)-\left(R_5\right)\to R_4 \end{gathered}$$
(2)Write After Read (WAR).
For example, in the following set of instructions, $I_3$The instruction should read $R_6$and store the content in the memory, and then $I_4$In the instruction, the operation result is written into $R_6$, That is to say, the reading command comes first, and the writing command comes after.
$$\begin{gathered} I_{3}MOVRESULT,R_6；(R6)\_\to RESULT \\ {I}_{4}SUB{R}_6,R_7,R_8；(R_7)-(R_8)\to R_6 \end{gathered}$$
(3)write after write (WAW).
In the following set of instructions, if $I_6$The AND result of the instruction is earlier than $I_5$The division result of the instruction becomes $I_6$Instructions at $I_5$Instruction write to $R_3$Write R 3 R_3 before$R_3$, resulting in $R_3$Content error, write-after-write related.
$$\begin{gathered} I_{5}DIV{R}_3,R_4,R_5；(R_4)÷(R_5)\to R_3 \\ {I}_{6}AND{R}_3,R_9,R_{10}；(R_9)AND(R_{10})\to R_3 \end{gathered}$$

8.11 Now there are four-stage pipelines, which respectively complete the four steps of fetching instructions (IF), decoding and fetching numbers (ID), executing (EX), and writing results (WR). Assume that the time to complete each step is 90ns, 90ns, 60ns, 45ns in turn.

(1) What value should the clock cycle of the pipeline take?
(2) If data correlation occurs in adjacent instructions, how long should the second instruction be delayed so that no error occurs?
(3) If data correlation occurs in two adjacent instructions, In order not to delay the execution of the second instruction, what measures can be taken?
Answer:
(1) The clock cycle of the pipeline should be considered according to the maximum time of each step operation, that is, the clock cycle of the pipeline should be 90ns.
(2) If data correlation occurs between two adjacent instructions, the execution of the second instruction needs to be suspended until the previous instruction produces a result before executing the second instruction, so at least two clock cycles must be delayed, that is, 180ns.
(3) If you want not to delay the execution of the second instruction, you can adopt bypass technology in hardware design, that is, set up a path for directly transmitting data. The main idea is that it is not necessary to wait for the execution result of an instruction to be sent back to the register, and then take the result out of the register as the source operand of the next instruction, but directly send the execution result to the place required by other instructions.

8.12 In an instruction pipeline with 5 functional segments, assume that the execution time of each segment is 10 ns, 8 ns, 10 ns, 10 ns and 7 ns. For a pipeline that completes 12 instructions, what is the speedup? What is the actual throughput of the pipeline?

answer:
Speedup ratio: The pipeline clock cycle is at least $10ns$ .
The time required for the pipeline to complete 12 instructions$(12-1)\times 10+5\times 10=160ns$ .$\_$
The time required to complete 12 instructions without pipeline$12\times (10+8+10+10+7)=540ns$。
Pipeline Speedup540 $540+160=3.375$ .
The actual throughput rate refers to the actual throughput rate of n instructions completed by the pipeline.
The actual leaf swallowing rate of this pipeline is$12/[(12-1)\times \Delta t+5\times \Delta t]$ and because$\Delta t=10ns$ , so the actual throughput rate:$0.075pieces/ns$

8.13 Why do super-long instruction words improve parallel processing capability more than superscalar?

Answer:
Both VLW technology and superscalar technology adopt an architecture in which multiple instructions are processed in parallel in multiple processing units, and how many instructions can flow out in one clock cycle.
butSuperscalar instructions come from the same standard instruction stream, the super-long instruction word is made by the compiler after digging out the potential parallelism among the instructions at compile time, and combines multiple instructions that can be operated in parallel into a super-long instruction with multiple opcode fields. Control multiple independently working functional parts in the ultra-long instruction word machine, and each opcode field controls a functional part, which is equivalent to executing multiple instructions at the same time, so the ultra-long instruction word technology has higher parallel processing capabilities than the standard other .

8.14 What do instruction pipelines and operation pipelines have in common in structure?

answer:
instruction pipelineThe entire execution process of the instruction is segmented by the pipeline. A typical instruction execution process is divided into several stages: fetching instructions, decoding instructions, forming addresses, fetching operands, executing instructions, writing back results, and modifying instruction pointers.
instruction pipeline and operation pipelinecommon groundYes: Since two adjacent segments are performing different operations, the required time may be different, so a latch or register must be set between adjacent two segments to ensure that the output signals of each segment of the pipeline are not the same within one clock cycle. Change.

8.15 What is an interrupt? What are the main issues to be considered when designing an interrupt system?

Answer:
During the running of the program, if the CPU encounters abnormal conditions or special requests, it needs to suspend the current program, turn to the processing of these abnormal conditions or special requests, and then return to the original program breakpoint to continue execution. process isto interrupt. The design of the interrupt system needs to consider the following issues.
(1) How the interrupt source makes a request to the CPU
(2) When multiple interrupt sources make requests at the same time, how does the CPU determine the priority of the response
(3) Under what circumstances (time, condition) does the CPU respond to the interrupt
(4) How to protect Site
(5) How to find the entry address of the interrupt service routine
(6) How to restore the site
(7) How to deal with interrupt nesting

8.16 In order to manage interrupts, what settings do computers usually have on the hardware? What are the functions of each? What are the considerations for the instruction system?

Answer:
In a computer system, in order to manage interrupts, the following hardware needs to be set up, and their functions are:
(1) Interrupt request triggers, the number of which is equal to the number of interrupt sources, used to mark a certain interrupt source item CPU Raise an interrupt request:
(2) Interrupt mask trigger, the number of which is equal to the interrupt request trigger, when it is 1, it means that the interrupt request of the interrupt source is masked, and the CPU cannot respond; (3) Queueer, used
to Perform interrupt arbitration. When multiple interrupt sources request at the same time, the queuer can select the interrupt request with the highest priority; (
4) The vector address forming part is used to generate the vector address of the interrupt source, so that the entry address of the interrupt service program can be found
(5) Allow Interrupt trigger, when it is 1, the CPU allows interrupt processing;
(6) Interrupt flag trigger, marking the system to enter the interrupt cycle;
(7) Stack, used to protect the scene;
(8) Interrupt query information number circuit. At the end of each instruction execution cycle, the circuit sends a query signal to each interrupt source. In the computer system, in order to manage interrupts, the instruction system should have instructions such as opening interrupts, closing interrupts, setting mask words, and interrupt return.

8.17 In the interrupt system, what are the functions of the three triggers INTR, INT, and EINT?

Answer:
INTR is an interrupt request trigger. Each interrupt source corresponds to an INTR. When it is "1", it means that the interrupt source has a request.
EINT is an enable interrupt trigger, when it is "1", it means that the CPU is allowed to respond to the request of the interrupt source; when it is "0", it means that the CPU is forbidden to respond to the interrupt.
INT is an interrupt flag trigger, when it is "1", it means that the CPU enters an interrupt cycle.

8.18 What is an interrupt implicit instruction and what are its functions?

Correct answer: The interrupt implicit instruction is an instruction that does not exist in the instruction system. It is automatically completed by the CPU during the interrupt response cycle. Its function is to protect the breakpoint of the program, close the interrupt by hardware, send the vector address to the PC (hardware vector method) or send the interrupt recognition program entry address to the PC (software query method).

8.19 What is the function of shielding technology in the interrupt system?

Answer:
The function of using shielding technology is:
(1) In a multi-interrupt system, after the CPU responds to an interrupt, it does not want to have interference from other low-level interrupt requests. Processing takes place reliably.
(2) Change the priority of interrupt processing.
(3) Selectively block some interrupt requests to make program control more flexible.

8.20 What hardware support is required to realize multiple interrupts?

Answer:
When the CPU is executing an interrupt service program, another interrupt source proposes a new interrupt request, and the CPU responds to this new request, temporarily stops the running service program, and turns to execute a new interrupt service program, this is called multiple interrupts, also known as interrupt nesting.
In order to achieve multiple interrupts, it is necessary to set up interrupt request triggers, mask triggers, queuers, vector address forming components, interrupt flag triggers, enable interrupt triggers, stacks, and interrupt query signal circuits.

8.21 How many ways can the CPU find the entry address of the interrupt service routine during the process of processing the interrupt? Give an example.

Answer:
There are two ways for the CPU to find the entry address of the interrupt service routine during interrupt processing.
(1) The hardware vector method is to generate a vector address corresponding to a certain interrupt source by a hardware circuit, and an unconditional transfer instruction can be set in the vector address to turn to the entry address of the interrupt service program. Just send the vector address to the PC in the interrupt response cycle, and when the CPU enters the next instruction fetch cycle, it can take out the unconditional transfer instruction, and execute the instruction to transfer to the interrupt service program. The entry address of the service program can also be directly stored in the vector address, and the entry address of the service program can be found by using the indirect address method by accessing the storage unit of the vector address.
(2) The software query method is to store a section of interrupt identification program in the main memory, which judges which interrupt source makes the request through the program, and transfers to the corresponding entry address. As long as the first address of the interrupt recognition program is sent to the PC in the interrupt response cycle, when the CPU enters the next instruction fetch cycle, the first instruction of the interrupt recognition program can be fetched, and the corresponding service program entry can be found by executing the instructions one by one. address.

8.22 Why is interrupt arbitration necessary during interrupt processing? There are several implementation methods? If you want to change the original priority order, what measures can you take?

Answer:
Any interrupt system can only respond to the request of one interrupt source at any time. However, many interrupt sources make requests at random. When multiple interrupt sources make interrupt requests at a certain moment, the interrupt system must respond according to their priority order, which is calledinterrupt arbitration。
The CPU can only respond to one interrupt at a timeTherefore, the arbitration must be interrupted to resolve the priority order of the corresponding responses.
There are two ways to implement interrupt arbitration:Hardware queuing and software queuing. The former is implemented with a combinational logic circuit, and the latter uses a program to query each interrupt source in order of priority (from high to low) to realize queuing.
To change the priority order, useshielding technology, reset the mask word, block the request source with high level, and open the request source with low level.

8.23 During the process of interrupt processing, what tasks need to be completed in "protecting the scene"? How to realize it?

Answer:
During interrupt processing, protecting the scene includes the following operations:
(1) Save the program breakpoint, which can be completed with the implicit interrupt command.
(2) Save the contents of each general-purpose register and status register, which can be programmed with machine instructions in the interrupt service routine.

8.24 There are 4 interrupt sources A, B, C, and D, and their priorities are arranged in the order of A→B→C→D from high to low. If the execution time of the interrupt service program is also 20μs, draw the trajectory of the CPU executing the program according to the moment when the interrupt source requests an interrupt given by the time axis shown in the figure below.

Answer:
The response priority of A, B, C, and D is the processing priority. The trajectory diagram of the CPU executing the program is as follows:

8.25 A machine has five interrupt sources $L_0、L_1、L_2、L_3、L_4$, sorted from high to low according to the priority of interrupt response as $L_0\to L_1\to L_2\to L_3\to L_4$, it is now required to change the interrupt processing sequence to $L_1\to L_4\to L_2\to L_0\to L_3$, It is now required to change the order of interrupt processing, according to the following format, write the mask word of each interrupt source.

Answer:
See the following table for the masking status of each interrupt source:

In the table: set the mask bit=1, which means masking; mask bit=0, means the interrupt is open.

8.26 Suppose a machine is equipped with A, B, and C3 devices, and their priorities are arranged in descending order of A→B→C. In order to change the order of interrupt processing, their interrupt mask words are set as follows:

equipment	masked word
A	1 1 1
B	0 1 0
C	0 1 1

Draw the trajectory of the CPU executing the program at the moment when the device requests an interrupt given by the time axis shown in the figure below. Suppose the execution time of A, B, and C interrupt service routines is $20\mu s$ .$\_$
answer:

8.27 Suppose a computer has 3 interrupt sources. Their priorities are arranged in descending order of 1→2→3. Suppose the interrupt processing time is $\tau$ , a total of 5 interrupt requests occurred within the time shown in the figure below. In the figure ① indicates that the interrupt request signal is issued by a level 1 interrupt source, and the rest are analogized to draw the trajectory of the CPU executing the program.

Answer:
According to the meaning of the question, the trajectory of the CPU executing the program is shown in the figure:

8.28 Suppose a computer has 4 interrupt sources 1, 2, 3, and 4, and their priorities are arranged in descending order of 1→2→3→4. Now it is required to change the order of interrupt processing to 4→1→3→2. According to the request time of the four interrupt sources given in the figure below, draw the trajectory of the CPU executing the program. Assume that the interrupt service routine time of the interrupt source is $20ms$ .

answer: