table of Contents
1. Overview of Window Watchdog
1. The difference between a window watchdog and an independent watchdog
1.1 Independent watchdog
Before talking about the window watchdog, let's briefly talk about the independent watchdog. Readers who want to learn more about the independent watchdog, please enter this link .
The main components of the independent watchdog include clock, down counter, key register, and reload register .
After the independent watchdog is started, the number in the down counter will be reduced by 1 every clock cycle until it is reduced to 0. The independent watchdog thinks that the program has run away, which will trigger a system reset ;
In order to prevent the watchdog from triggering a reset, we need to tell the watchdog "The program has not run away and is still under my control ". How do we notify the watchdog of this message? We need to send a load signal to the key register . After the key register receives the signal, it will instruct the reload register to assign the value it loaded to the down counter to update the down counter.
As long as we ensure that the value in the decrement counter is updated before it reaches 0 , we can ensure that the watchdog will not trigger a reset. This operation is what we often call " feeding the dog ".
The schematic diagram is roughly as follows, please forgive me if OneNote is not used well...
1.2 Window watchdog
Window watchdog, its most important components are still clock, down counter, key register, reload register , and the key lies in its understanding window .
Window window watchdog refers upper time limit / upper window and lower time / the window , wherein:
① upper limit time and limit time is actually two different values in the process from the initial start descending down counter, the two will go through these values.
② down counter initial value> upper limit time> time limit
The upper limit time and the lower limit time have different functions:
- After starting the window watchdog, the decrement counter starts to decrement from the initial value;
- If the user reloads the value of the down counter before it reaches the upper limit time , it will cause the system to reset ;
- If during the window when the upper limit time is reduced to the lower limit time , the user reloads the value of the down counter , then this is a normal feeding dog , and the program runs normally without resetting ;
- If the user still does not feed the dog when the time is reduced to the lower limit , then the effect of reducing the independent watchdog to 0 will be the same , and the system will be reset .
Note: The lower limit time is not 0 , and its value is fixed by the system, which is 0x3F .
The internal structure diagram of the attached window watchdog is as follows:
The workflow diagram is roughly as follows:
1.3 Window watchdog can cause interrupt
The window watchdog can cause an interrupt, and the user can feed the dog in the interrupt service function.
The independent watchdog cannot cause an interrupt.
1.4 Different clock sources and accuracy
The original clock signal of the independent watchdog comes from LSI, which is an independent clock, but the frequency is low and the accuracy is low.
The clock of the window watchdog comes from PCLK1, not an independent clock, but with high frequency and high precision.
2. The working details of the window watchdog
2.1 When is it appropriate to feed the dog?
As mentioned above, the lower limit time is a fixed value, 0x3F , which is binary 011 1111 .
Then, in the down counter from 1 million reduced to 0,111,111 the moment, that is about to initiate a reset before the moment, the window will first trigger watchdog interrupt (interrupt if it has been enabled), the user can interrupt service function in Write a program to feed the dog .
2.2 The counter and the control register work together to generate an interrupt
As mentioned above, at the moment when 100 0000 is decremented to 011 1111 , an interrupt will be triggered. In fact, as long as the sixth bit of this binary number (counting from 0) has changed from 1 to 0 , it can be judged whether To cause an interruption.
The schematic diagram of the counter is as follows:
As you can see, the counter has eight bits, namely T0, T1, T2, T3, T4, T5, T6 , which are used for counting ; and a WDGA , which is used to enable the window watchdog.
The system ( window watchdog control register WWDG_CR ) only needs to detect whether the T6 bit has changed from 1 to 0, and it can know whether to trigger an interrupt.
3. Window watchdog timeout calculation
①Calculation of frequency division coefficient:
When the frequency division register is set to WDG_TB , the actual frequency division coefficient is `
4096 x ( 2 ^ WDG_TB)
Since the original clock of the window watchdog is received from PCLK, the frequency is very high (accurate), so it must be fixed by dividing it by 4096 to reduce its frequency; then dividing by 2 ^ WDG_TB for further frequency division .
According to the frequency division coefficient and the original frequency Fpclk, the new clock period of the new clock signal can be obtained as the reciprocal of the new clock frequency **, namely:
4096 x ( 2 ^ WDG_TB) / Fpclk
②The initial value of the clock cycle x decrement counter:
The watchdog timeout time refers to 递减计数器减到下限时间所用的总时间, so after getting the clock cycle ( decrement counter minus 1 every clock cycle ), multiply the initial value of the down counter to get the final window watchdog timeout time, namely:
4096 x ( 2 ^ WDG_TB) x (T[5:0] + 1)/ Fpclk
In the above formula T[5:0] + 1 , **T[5:0]** refers to the 0 ~ 5 bits of the binary initial value of the down counter, why not take the 6th bit?
Because what we want is the value from the initial value to the lower limit time, and the down counter has a total of 6 bits, the lower limit time is 011 1111, and after adding 1 to get 100 0000; and the initial value of the down counter is 1xx xxxx, use 1xx xxxx to decrement Going to 100 0000, the result is naturally 0 to 5 bits, that is, T[5:0], that is, xx xxxx.
Adding 1 on this basis is to make up for the 1 count from 100 0000 to 011 1111.