Preface
When you use a microcontroller to develop a specific product, in order to ensure the reliability of the software, in addition to a series of frameworks and flow charts, etc., you also need a mechanism similar to regular checks to ensure that our MCU is operating normally according to your software. The logic is running, this is the watchdog module in our microcontroller function.
watchdog
1. Introduction
The watchdog timer (WDGT) is a hardware timing circuit used to monitor system failures caused by software failures. There are two watchdog timer peripherals on the chip, the independent watchdog timer (FWDGT) and the window watchdog timer (WWDGT). They are flexible to use and offer a high level of security and precise time control. Both watchdog timers are used to solve
software failure problems.
The watchdog timer will trigger a reset (for the window watchdog timer, an interrupt will be generated) when the internal count value reaches the preset threshold. The watchdog timer can stop counting when the processor is in debug mode.
————The above is excerpted from the watchdog timer chapter of the GD32F303 user manual
2. Difference
The ultimate goal of both is the same thing - regular checks and automatic reset in case of abnormality. The difference is that the clock sources of the two are different.
Independent watchdog : The clock source comes from the internal low-speed clock . Therefore, even if the main clock fails, a reset is guaranteed to occur. But the counting accuracy is not high.
Window watchdog : The clock source comes from the APB1 clock prescaler . This ensures accurate counting, but if the main clock fails, it will also fail.
For most products, the watchdog we need is a function of regular check and reset, and the counting accuracy is not particularly important (for example, 1s becomes 1.01s). The sample code given in this article also configures an independent watchdog .
Programming of each module
Before configuring, please make sure you already have a GD32F303 keil project that includes its corresponding standard library . The project can be created using official routines or according to the project creation and compilation of GD32F303 Debugging Notes (Zero) .
1. Independent watchdog timer block diagram
2. Precautions
- The focus is on the red box in the above picture, so I won’t explain it here.
3. Initialization configuration
void FWDGT_Init(void)
{
uint16_t timeout_t=0xFFFFU;
/* enable IRC40K */
rcu_osci_on(RCU_IRC40K);
/* wait till IRC40K is ready */
while(SUCCESS != rcu_osci_stab_wait(RCU_IRC40K))
{
if(timeout_t > 0) timeout_t--;
else break;
}
/* configure FWDGT counter clock: 40KHz(IRC40K) / 64 = 0.625 KHz */
fwdgt_config(2*500,FWDGT_PSC_DIV64); //t = (1/0.625)x(2x500) = 1.6s
fwdgt_write_disable();
/* After 1.6 seconds to generate a reset */
fwdgt_enable();
}
- Turn on the internal low-speed clock, wait for stabilization, configure the watchdog timer frequency division coefficient and reload count value, turn on the watchdog register write protection function, and turn on the door dog timer.
4. Main function
1. Create a dog feeding task
- Turn off the watchdog write protection and reload the count value.
void task_fwdgt_reload(void)
{
/* uncock fwdgt write protect*/
fwdgt_write_enable();
/* feed fwdgt */
fwdgt_counter_reload();
}
2. Main function
- You can feed the dog task as a subtask in the scheduling system, or as a must-do thing in the largest loop in pure bare metal, like this:
int main(void)
{
FWDGT_Init();
while(1)
{
task_fwdgt_reload();
}
}
3. Others
- Once the watchdog is turned on, it cannot be turned off. However, the reload value can be modified, that is, the watchdog is artificially overflowed and the entire software system is reset. as follows:
/* 某种条件触发 */
if(something)
{
/* 重新配置看门狗计数值 */
fwdgt_write_enable();
/* configure FWDGT counter clock: 40KHz(IRC40K) / 64 = 0.625 KHz */
fwdgt_config(5,FWDGT_PSC_DIV64); //t = (1/0.625)x(5) = 8ms
fwdgt_counter_reload();
fwdgt_enable();
}