[Learning Record] STM32 watchdog experiment

Why watchdog?

        In a microcomputer system composed of a single-chip microcomputer, the work of the single-chip microcomputer is often interfered with by external electromagnetic fields, causing the program to run away and fall into an infinite loop. The normal operation of the program is interrupted, and the system controlled by the single-chip microcomputer cannot continue to work. , will cause the entire system to stagnate and produce unpredictable consequences . Therefore, out of the consideration of real-time monitoring of the running status of the single-chip microcomputer, a module or chip specifically used to monitor the running status of the single-chip microcomputer program has been produced , commonly known as " watching ". "door dog " (watchdog) .

What problem does a watchdog solve?

        While starting normal operation, the system cannot be reset.

        In the case of system runaway (abnormal execution of the program), the system is reset and the program is executed again.

Watchdog Overview

        STM32 has two built-in watchdogs, providing higher security, time accuracy and   flexibility of use. Two watchdog devices (independent watchdog / window watchdog ) can be used to detect and resolve failures caused by software errors. When the counter reaches a given timeout value, an interrupt is triggered (window watchdog only) or a system reset is generated.

        The independent watchdog (IWDG) is driven by a dedicated low-speed clock ( LSI) , and it is still valid even if the main clock fails .  The independent watchdog is suitable for applications that require the watchdog to work outside the main program and require low time precision.

        The window watchdog (WWDG) is driven by a clock divided from the APB1 clock. Detect abnormally late or premature application operation with a configurable time window. Windowed watchdogs are best suited for programs that require the watchdog to function during precisely timed windows.

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Independent Watchdog Experiment (IWDG) Experiment

Functional Overview:

        Write 0xCCCC in the key value register ( IWDG_KR) to enable the independent watchdog. At this time, the counter starts to decrement from its reset value 0xFFF , and a reset signal ( IWDG_RESET) will be generated when the counter value counts to the tail value 0x000 .

        Whenever 0xAAAA is written to the key value register IWDG_KR (usually called dog feeding) , the value of the automatic reload register IWDG_RLR will be reloaded into the counter, thereby avoiding a watchdog reset.

        If the program is abnormal, the dog cannot be fed normally, and the system is reset.

Independent watchdog block diagram

        Key value register IWDG_KR: 0~15 bits are valid

Prescaler register IWDG_PR: 0~2 bits are valid. With write protection function, cancel the write protection before operation

Reload register IWDG_RLR: Bits 0~11 are valid. With write protection function, cancel the write protection before operation

Status register IWDG_SR: bits 0~1 are valid

Independent watchdog timeout

Overflow time calculation:

   All=((4 × 2^prer) × rlr ) /40 （M3)

Clock frequency LSI=40K, one watchdog clock cycle is the shortest time-out time.

Maximum timeout time = (IWDG_RLR register maximum value) X watchdog clock period

IWDG independent watchdog operation library function

void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);//Cancel write protection: 0x5555 enable

void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);//Set the prescaler coefficient: write PR

void IWDG_SetReload(uint16_t Reload);//Set reload value: write RLR

void IWDG_ReloadCounter(void);//feed the dog: write 0xAAAA to KR

void IWDG_Enable(void);//Enable watchdog: write 0xCCCC to KR

FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);//Status: reload/prescaler update

Independent watchdog operation steps

①Cancel register write protection:

IWDG_WriteAccessCmd ();

② Set the prescaler coefficient of the independent watchdog to determine the clock:

IWDG_SetPrescaler ();

③ Set the watchdog reload value to determine the overflow time 

IWDG_SetReload ();

④ Enable watchdog:

IWDG_Enable ()

⑤ Application to feed dogs:

IWDG_ReloadCounter ();

Overflow time calculation: Tout=((4 × 2^prer) × rlr ) /40 ( M3)

Practical exercise:

 

 The result of this program: the red light flashes once every 200ms in the state of no operation, and the light remains constant after pressing the KEY_UP button

 

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Window Watchdog Experiment (WWDG)

Overview:

It is called a window because the dog feeding time is within a range (window) with an upper and lower limit. You can set the upper limit time (the lower limit is fixed) by setting the relevant registers. Feed your dog neither too early nor too late.

The independent watchdog limits the feeding time to 0-x, and x is determined by the relevant register. Don’t feed your dog too late.

Working diagram

 Window watchdog block diagram:

 

There is a 7- bit decrement counter T[6:0] in the window watchdog of STM32F , which will generate a watchdog reset when one of the following two situations occurs:

①When feeding the dog, if the counter value is greater than a certain set value W[6:0] , this set value is defined in the WWDG_CFR register.

② When the value of the counter decreases from 0x40 to 0x3F [T6 bit jumps to 0] .

If the watchdog is enabled and interrupts are enabled, an early wake-up interrupt ( EWI) is generated when the down counter equals 0x40 , which can be used to feed the dog to avoid a WWDG reset.

Window watchdog timeout

Why a window watchdog?

        For general watchdogs, the program can refresh the watchdog at any time before it is reset, but there is a hidden danger. It is possible that the program runs out of order and then returns to the normal place, or the out-of-order program happens to be executed. Refresh the watchdog operation, in this case, the general watchdog will not be able to detect it;

       If a window watchdog is used, the programmer can set a time window to refresh the watchdog according to the normal execution time of the program to ensure that the watchdog will not be refreshed in advance or delayed, so that it can be detected that the program does not follow the instructions. The normal path operation skips certain program sections abnormally.

Precautions:

①The upper window value W[6:0] must be greater than the lower window value 0x40. Otherwise there will be no window.

②Window watchdog clock source PCLK1 (APB1 bus clock) after frequency division

Window watchdog configuration process

①Enable watchdog clock:

RCC_APB1PeriphClockCmd();

② Set frequency division coefficient:

WWDG_SetPrescaler ();

③Set the upper window value:

WWDG_SetWindowValue ();

④Enable early wake-up interrupts and group them ( optional ):

WWDG_EnableIT ();  

NVIC_Init ();

⑤ Enable watchdog:

WWDG_Enable ();

⑥ Feeding the dog :

WWDG_SetCounter ();

⑦Write interrupt service function:

WWDG_IRQHandler ();

Important code snippet:

stm32f10x.wwdg_h

 etc. h

etc. c 

main.c 

After downloading the program, the green light flashes, and it stops after pressing the KEY_0 button, and the red light flashes when the button is released.

After the button process is completed, the green light continues to flash.