1, WWDG Profile
Window watchdog (the WWDG) is commonly used to detect interference generated by the external departing unforeseen or application logic condition caused by normal operating sequence of software failures.
WWDG is a constantly diminishing down counter. When the counter is decremented to a fixed value WWDG 0x40, yet again assigned a count value (known as feed the dog), it will generate a reset signal to the reset and fixed value 0x40 is called the lower limit of the window, the lower limit of the window no need to set the value.
WWDG there is a limit on the window, when the counter value is larger than the upper limit value WWDG window, if re-assignment to WWDG counter (DOG), will produce a reset signal to reset the chip, the upper limit of the window value can be set by a program.
That is when using the WWDG, to WWDG counter reassignment can not be too early, nor too late to be able to be within a certain period of time.
2, WWDG time calculation
WWDG APB1 is mounted on the peripheral bus, the clock source of WWDG PCLK1. Note that when PCLK1 WWDG to provide a clock source have been 4096 crossover, this divide is the default chip, can not be changed. So WWDG clock source should be PCLK1 / 4096.
Since WWDG not IWDG as an independent clock source when using WWDG, you need to make the clock can WWDG otherwise unusable.
WWDG clock can be frequency-divided, by configuring WWDG_CFR arranged BIT8 ~ BIT7 register bit is WDGTB [1: 0] can be frequency-divided clock from PCLK1 / 4096, as follows:
- WDGTB [1: 0] = 00: WWDG counter clock from PCLK1 / 4096 and then divided by one.
- WDGTB [1: 0] = 01: WWDG counter clock from PCLK1 / 4096 and then divided by two.
- WDGTB [1: 0] = 10: WWDG counter clock from PCLK1 / 4096 and then divided by four.
- WDGTB [1: 0] = 11: WWDG counter clock from PCLK1 / 4096 and then divided by eight.
WWDG clock so calculated as follows:
WWDG_CLK = PCLK1/(4096*PR)
PCLK1 is APB1 bus clock, PR is WWDG division factor.
Having reached the size of the WWDG clock, it can be calculated WWDG counter decremented each time elapsed, as follows:
Step_time = 1/WWDG_CLK = (4096*PR)/PCLK1
If PCLK1 unit is MHZ, then the calculated level of the unit is us; if PCLK1 units of KHZ, then the calculated unit is ms level.
Suppose PCLK1 = 36MHZ, then the minimum time-out time WWDG:
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- When WDGTB = 0, the minimum timeout WWDG as: time = (4096 * 1) / 36 (us) = 113 (us).
- When WDGTB = 1, the minimum timeout WWDG as: time = (4096 * 2) / 36 (us) = 227 (us).
- When WDGTB = 2, the minimum time-out time is WWDG: time = (4096 * 4) / 36 (us) = 455 (us).
- When WDGTB = 3, the minimum time-out time WWDG as: time = (4096 * 8) / 36 (us) = 910 (us).
After obtaining WWDG counter decremented every elapsed time, but also the number of down counter is calculated from the initial value WWDG WWDG counter and the fixed value 0x40. Suppose the initial value is set to X, then WWDG reset signal generation time is calculated as follows:
Twwdg = ((4096*PR)/PCLK1)*(X - 0x40)
3, WWDG window value
3, WWDG configuration process