Verilog Notes. 5. Synchronous, Asynchronous

In digital circuits, there are often concepts of synchronous and asynchronous. Asynchronous means that the input signal has nothing to do with the clock; synchronous means that the input signal is related to the clock signal, in fact, the input signal and the clock signal are ANDed or NANDed. In actual development, there are often concepts such as synchronous clearing, asynchronous clearing, synchronous reset, and asynchronous reset. The relevant code demonstrations are given below.

 

Simple asynchronous reset

1 always @ (posedge clk or negedge rst_n)
2          if(!rst_n) b <= 1'b0;
3          else b <= a;

Simple synchronous reset

1 always @ (posedge clk)
2          if(!rst_n) b <= 1'b0;
3          else b <= a;

PS: The synchronous reset signal RST must be at least longer than one clock cycle CLK, otherwise, the change caused by this reset signal will not be detected!

 

Asynchronous reset, synchronous release

1  always @ ( posedge clk)
 2           rst_nr <= rst_n;                  // Now beat the asynchronous reset signal with the synchronous clock 
3  
4  always @ ( posedge clk or  negedge rst_nr)
 5           if (!rst_nr) b <= 1 ' b0; 
6           else b <= a;
 7  
8  always @ ( posedge clk or  negedge rst_nr)
 9           if (!rst_nr) c <= 1 ' b0; 
10           else c <= b;

 

The difference between synchronous reset and asynchronous reset is that the complex signal of the former cannot appear in the sensitive signal table of the always statement. Whether it is a synchronous reset or an asynchronous
reset, the structure of the always statement is if(Reset)...else... , otherwise, the synthesis tool will not synthesize correctly

All assignments in always statements are preferably non-blocking assignments, otherwise, it may lead to inconsistencies between simulation and synthesis"