Preface: The content of this chapter is mainly to demonstrate the circuit design, simulation, synthesis and download using Verilog language under Vivado
Example: Encoder/Decoder Application
- Features: Using Xilinx Artix-7 XC7A35T chip
- Configuration method: USB-JTAG/SPI Flash
- Up to 100MHz internal clock speed
- Memory: 2Mbit SRAM N25Q064A SPI Flash (the old model of the sample picture is N25Q032A)
- General IO: Switch: x8LED: x16Button: x5DIP: x8 General expansion IO: 32pin
- Audio and video/display: 7-segment digital tube: x8 VGA video output interface Audio audio interface
- Communication interface: UART: USB to UART Bluetooth: Bluetooth module
- Analog interface: DAC: 8-bit resolution XADC: 2-way 12bit 1Msps ADC
Table of contents
0x00 3-8 Decoder 74LS138 working principle
0x01 The working principle of priority encoder 74148
Ⅰ. Pre-requisite knowledge
0x00 3-8 Decoder 74LS138 working principle
Use the IP package provided by Vivado (as shown in the figure below)
You can also directly (see the following code) build a 74LS138 function verification circuit.
(1) When the gate e1 is at high level and the other two gates e2 and e3 are at low level, the chip is enabled. The binary code of the address terminal (a2, a1, a0) is decoded at the output terminal corresponding to y0 to y7 with a low level. For example: when a2a1a0=110, y6 outputs a low level signal.
(2) Using e1, e2 and e3 can be conveniently cascaded and expanded into 16-line decoder and 32-line decoder.
(3) If one of the strobe terminals is used as a data input terminal, the 74LS138 can also be used as a data distributor
Test 74LS138 logic relationship wiring diagram
Use verilog programming to realize the decoding function, the reference code is as follows. The enable signal in the reference program needs to be completed by itself.
module converter(DB,SEG);
input[2:0] DB;
output[7:0] SEG;
reg[7:0] SEG;
always @(DB)
begin
case(DB)
4'b0000: SEG<=8'b11111110;
4'b0001: SEG<=8’b11111101;
4'b0010: SEG<=8’b11111011;
4'b0011: SEG<=8’b11110111;
4'b0100: SEG<=8’b11101111;
4'b0101: SEG<=8’b11011111;
4'b0110: SEG<=8’b10111111;
4'b0111: SEG<=8’b01111111;
default: SEG<=8'b11111111;
endcase
end
endmodule 0x01 The working principle of priority encoder 74148
In the priority encoder circuit, more than two encoded signals are allowed to be input at the same time.
However, when designing a priority encoder, all input signals have been queued in order of priority. When there are two or more input signals at the same time, the priority encoder only encodes the input signal with high priority, and the signal with low priority does not work.
The 74148 is an 8-3 wire priority encoder. The 74148 priority encoder is a 16-pin integrated chip, except for the power pin VCC (16) and GND (8), the functions and pin numbers of the other input and output pins are marked in the figure.
Among them, i0~i7 are input signals (i7 has the highest priority), qc, qb, and qa are three-digit binary coded output signals, ei is the enable input terminal, eo is the enable output terminal, and gs is the chip priority coded output terminal.
The circuit wiring is shown in the figure below:
Encoder Wiring
Use verilog programming to realize the priority coding function, the reference code is as follows:
module encoder_83 (din, EI, GS, EO, dout);
input [7:0] din; //编码输入端data_in，低电平有效
input EI; //使能输入端EI（选通输入端），EI为 0 时芯片工作,即允许编码
output [2:0] dout; //编码输出端data_out
output GS; //片优先编码输出端，优先编码器工作工作状态标志GS，低电平有效
output EO; //使能输出端EO（选通输出端）
reg [2:0] dout;
reg GS, EO;
always @(din or EI)
if(EI) begin dout <= 3'b111; GS <= 1; EO <= 1; end //所有输出端被锁存在高电平
else if (din[7] == 0) begin dout <= 3'b000; GS <= 0; EO <= 1; end
else if (din[6] == 0) begin dout <= 3'b001; GS <= 0; EO <= 1; end
else if (din[5] == 0) begin dout <= 3'b010; GS <= 0; EO <= 1; end
else if (din[4] == 0) begin dout <= 3'b011; GS <= 0; EO <= 1; end
else if (din[3] == 0) begin dout <= 3'b100; GS <= 0; EO <= 1; end
else if (din[2] == 0) begin dout <= 3'b101; GS <= 0; EO <= 1; end
else if (din[1] == 0) begin dout <= 3'b110; GS <= 0; EO <= 1; end
else if (din[0] == 0) begin dout <= 3'b111; GS <= 0; EO <= 1; end
else if (din == 8'b11111111) begin dout <= 3'b111; GS <= 1; EO <= 0; end //芯片工作，但无编码输入
else begin dout <= 3'b111; GS <= 1; EO <= 1; end //消除锁存器（latch）
endmodule
//EI = 0 表示允许编码，否则所有输出端被封锁在高电平（控制芯片工作）
//EO = 0 表示电路工作，但无编码输入（用于级联）
//GS = 0 表示电路工作，且有编码输入（判断输入端是否有输入）Ⅱ. Verilog implementation
0x00 priority encoder 74LS148
Design code:
module encoder1(n_EI,n_I,n_Y,n_CS,n_E0);
input n_EI;
input [7:0] n_I;
output [2:0] n_Y;
output n_CS,n_E0;
reg [2:0] n_Y;
reg n_CS,n_E0;
always @(n_EI or n_I)
if(n_EI==0)
if(n_I[7]==0){n_CS,n_E0,n_Y}=5'b0_1_000;
else if(n_I[6]==0){n_CS,n_E0,n_Y}=5'b0_1_001;
else if(n_I[5]==0){n_CS,n_E0,n_Y}=5'b0_1_010;
else if(n_I[4]==0){n_CS,n_E0,n_Y}=5'b0_1_011;
else if(n_I[3]==0){n_CS,n_E0,n_Y}=5'b0_1_100;
else if(n_I[2]==0){n_CS,n_E0,n_Y}=5'b0_1_101;
else if(n_I[1]==0){n_CS,n_E0,n_Y}=5'b0_1_110;
else if(n_I[0]==0){n_CS,n_E0,n_Y}=5'b0_1_111;
else{n_CS,n_E0,n_Y}=5'b1_0_111;
else{n_CS,n_E0,n_Y}=5'b1_1_111;
endmodule
Simulation test code:
module sim_encoder1();
reg n_EI;
reg [7:0] n_I;
wire [2:0] n_Y;
wire n_CS,n_E0;
encoder1 test(.n_EI(n_EI),.n_I(n_I),.n_Y(n_Y),.n_CS(n_CS),.n_E0(n_E0));
always begin
n_EI=1'b0;n_I=8'b01111111;#100;
n_EI=1'b0;n_I=8'b10111111;#100;
n_EI=1'b0;n_I=8'b11011111;#100;
n_EI=1'b0;n_I=8'b11101111;#100;
n_EI=1'b0;n_I=8'b11110111;#100;
n_EI=1'b0;n_I=8'b11111011;#100;
n_EI=1'b0;n_I=8'b11111101;#100;
n_EI=1'b0;n_I=8'b11111110;#100;
end
endmodule
Waveform diagram:
0x01 3-8 decoder
Design code:
module encoder(B,SEG,en);
input[2:0] B;
input[2:0] en;
output[7:0] SEG;
reg[7:0] SEG;
always @(B or en)
if(en[2]&(~en[1])&(~en[0]))
case(B)
3'b000: SEG=8'b11111110;
3'b001: SEG=8'b11111101;
3'b010: SEG=8'b11111011;
3'b011: SEG=8'b11110111;
3'b100: SEG=8'b11101111;
3'b101: SEG=8'b11011111;
3'b110: SEG=8'b10111111;
3'b111: SEG=8'b01111111;
default: SEG=8'b11111111;
endcase
else SEG=8'b11111111;
endmodule
Simulation test code:
module sim_encoder();
reg [2:0]B;
reg [2:0]en;
wire [7:0]SEG;
encoder test(.B(B),.SEG(SEG),.en(en));
always begin
en=3'b100;B=3'b000;#100;
en=3'b100;B=3'b001;#100;
en=3'b100;B=3'b010;#100;
en=3'b100;B=3'b011;#100;
en=3'b100;B=3'b100;#100;
en=3'b100;B=3'b101;#100;
en=3'b100;B=3'b110;#100;
en=3'b100;B=3'b111;#100;
end
endmoduleWaveform diagram:
0x02 result data
74LS138 Function Table
| enter |
output |
||||||||||||
| Enable |
choose |
||||||||||||
| e1 (G1) |
e2（G2B） |
e3（G2A） |
a2(C) |
a1(B) |
a0(A) |
y7 |
y6 |
y5 |
y4 |
y3 |
y2 |
y1 |
y0 |
| 0 |
× |
× |
× |
× |
× |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| 1 |
× |
1 |
× |
× |
× |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| 1 |
1 |
× |
× |
× |
× |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| 1 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
| 1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
| 1 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
| 1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
| 1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
| 1 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
| 1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
| 1 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
Priority Encoder 74LS148 Function Table
| enter |
output |
||||||||||||
| enable |
i7 |
i6 |
i5 |
i4 |
i3 |
i2 |
i1 |
i0 |
qc |
qb |
qa |
eo strobe |
gs expand |
| 1 |
× |
× |
× |
× |
× |
× |
× |
× |
1 |
1 |
1 |
1 |
1 |
| 0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| 0 |
0 |
× |
× |
× |
× |
× |
× |
× |
0 |
0 |
0 |
1 |
0 |
| 0 |
1 |
0 |
× |
× |
× |
× |
× |
× |
0 |
0 |
1 |
1 |
0 |
| 0 |
1 |
1 |
0 |
× |
× |
× |
× |
× |
0 |
1 |
0 |
1 |
0 |
| 0 |
1 |
1 |
1 |
0 |
× |
× |
× |
× |
0 |
1 |
1 |
1 |
0 |
| 0 |
1 |
1 |
1 |
1 |
0 |
× |
× |
× |
1 |
0 |
0 |
1 |
0 |
| 0 |
1 |
1 |
1 |
1 |
1 |
0 |
× |
× |
1 |
0 |
1 |
1 |
0 |
| 0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
× |
1 |
1 |
0 |
1 |
0 |
| 0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
、