When talking about the future of wearable technology, it clearly shows the future progress of wearable technology innovation. It is loud and clear that, in order to be successful, wearable electronics must be small while maintaining performance.
In order to reduce the footprint and thus reduce the overall board space, microcontrollers are migrated to smaller process nodes every generation. At the same time they are evolving to perform more complex and powerful operations. As operations become more complex, there is an urgent need to increase the cache. Unfortunately for each new process node, adding embedded cache (embedded SRAM) becomes challenging for many reasons, including higher SER, lower yield, and higher power consumption. Customers also have customized SRAM requirements. For MCU manufacturers, to provide all possible cache sizes will require them to have a product portfolio that is too large to manage. This drives the need to limit the embedded SRAM on the controller die and cache via external SRAM.
However, because the external SRAM takes up a lot of board space, the use of external SRAM faces the challenge of miniaturization. Due to its six-transistor structure, reducing the size of the external SRAM by transplanting the external SRAM to a smaller process node will bring the same problems that plague the miniaturized embedded SRAM.
This brings us to the next alternative to this ancient problem: reducing the ratio of chip package to chip size in external SRAM. Usually the size of the packaged SRAM chip is many times the size of the die (maximum 10 times). A common way to solve this problem is to not use packaged SRAM chips at all. It makes sense to take SRAM chips (1/10 size, and then use complex multi-chip packaging (MCP) or 3D packaging technology (also called SiP or system-in-package) to package it with the MCU chip. But this The method requires a lot of investment and is only feasible for the largest manufacturers. From a design point of view, this also reduces flexibility because the components in SiP are not easy to replace. For example, if there is a new technology SRAM available, we cannot SRAM chips can be easily replaced in SiP easily. To replace any die in the package, the entire SiP must be re-qualified. Re-qualification requires reinvestment and more time.
So is there a way to save board space while at the same time excluding SRAM from the MCU without causing MCP to get into trouble? Going back to the ratio of die to chip size, we do see room for significant improvement. Why not check if there is a packaging that can fit the mold? In other words, if you cannot cancel the packaging, please reduce the size ratio.
The current most advanced method is to reduce the chip size of the package by using WLCSP (Wafer Level Chip Scale Packaging). WLCSP refers to a technology in which a single unit is cut from a wafer into small pieces and then assembled in a package. The device is essentially a bare chip with bumps or spherical array patterns, without any bonding wires or interposer connections. According to specifications, the area of the chip-scale package component is up to 20% larger than the chip. Now that the process has reached an innovative level, the manufacturing plant can produce CSP devices without increasing the chip area (only slightly increased thickness to suit bumps/balls).
digital. Wafer-level chip-scale packaging (WLCSP) provides the most advanced method of reducing package die size. The WLCSP shown here was developed by Deca Technologies and will not increase the area of the chip that composes it. (Source: Deca Technologies/Cypress Semiconductor)
CSP has certain advantages over bare chips. CSP equipment is easier to test, handle, assemble and rewrite. They also have enhanced thermal conductivity properties. When the die is transferred to a newer process node, the size of the CSP can be standardized while the die is reduced. This ensures that CSP components can be replaced by a new generation of CSP components without any complexity caused by mold replacement.
Obviously, these space savings are very important in terms of the demand for wearable devices and portable electronic products. For example, the 48-ball BGA used by the memory in many wearable devices today has a size of 8mmx6mmx1mm (48mm3). In contrast, the size of the same part in the CSP type package is 3.7mmx3.8mmx0.5mm (7mm3). In other words, the volume can be reduced by 85%. This saving can be used to reduce the PCB area and thickness of portable devices. Therefore, the demand for WLCSP-based devices from wearable devices and Internet of Things (IoT) manufacturers is not only limited to SRAM, but also has new requirements.