concept
Static random access memory (Static Random-Access Memory, SRAM) is a random access memory. So-called "static", refers to such a memory as long as power remains, which stored data can be maintained invariant. By contrast, a dynamic random access memory (DRAM) which requires the stored data is periodically updated. However, when the power supply is stopped, the data stored in SRAM or disappear (to be referred to volatile memory), flash memory or ROM which can store data after power failure is different.
-6 transistor memory structure
6T: refers to the six transistors, as shown by M1, M2, M3, M4, M5, M6 of each bit stored in the SRAM of four FET (M1, M2, M3, M4). constitute two cross-coupled inverters. Further two FET (M5, M6) is a basic unit of storage to read and write bit lines (BitLine) control switch.
A base unit constituting the inverter mos
6T is equivalent to the circuit SR latch
----- "BL (non) and M5, Q (non), M4, M3 composed of a NAND gate, BL, M6, Q, M2 , M1 form another NAND gate
SRAM cell design of a basic SRAM has two levels of 0 and 1 stable state. The basic SRAM cell consists of two CMOS inverters. Two input inverter, cross-connect output, i.e. the output of the first inverter is connected to a second input inverter, the output of the first inverter connected to the input of the second inverter. This makes it possible to achieve locking of the two inverters output state, saved, stored 1-bit state. In addition to SRAM tube. 6, there are other SRAM 8, 10 or even more per bit implemented using transistors. This can be used to read and write multi-port (Port) access, such as memory or register file to achieve a multi-port SRAM circuit. In general, the fewer number of transistors used in each basic unit, the smaller the area it occupies. Since silicon (silicon wafer) production costs are relatively fixed, so the smaller the area of the basic SRAM cell, the silicon chip can be manufactured more memory bits, the lower the cost per bit of storage.
The basic unit of memory used is less than six transistors are possible - such as three or even single tube, but the single tube storage unit be DRAM, not SRAM.
SRAM operation
When accessing SRAM, a word line (Word Line) H-level, so that the two control switches each basic cell transistor M5 and M6 with the opening of the base unit in communication with a bit line (Bit Line). A bit line for reading or writing the saved state of the base unit. Although not required, the anti-two lines to take place, but this inverted bit line helps to improve noise margin.
The basic SRAM cell has three states:. Standby (idle circuit), reading (read) and Writing (content)
of the SRAM read or write mode must be "readability" (read) and "write stability", respectively (Write stable).
Standby
如果字线没有被选为高电平, 那么作为控制用的M5与M6两个晶体管处于断路，把基本单元与位线隔 离。由M1 – M4组成的两个反相器继续保持其状态，只要保持与高、低电平的连接。
Reading
假设cell中保存的数据是1（Q点是高电平），当进行读操作的时候，首先把两根bit line（BL和BL）设置为高电平。之后assert WL，以便导通M5和M6。M5和M6导通之后，我们分成两个部分来看。右边的BL和Q都是高电平，因此状态不变。对于左边，BL是高电平，而Q是低电平，这时候，BL就会通过M5、M1进行放电，如果时间足够长，BL最终会变成低电平。cell保存数据0的情况是类似的，只不过这时候最终BL会保持高电平，而BL最终会被放电成低电平，具体的过程这里不再详述。BL和BL会接到sense amplifier上，sense amplifier可以感知BL和BL之间的电压差从而判断cell中保存的是0还是1。
Writing
write cycle at the beginning, to write to the state of the bit line load. If writing 0, is set (non BL) and BL is 0 to 1. Then loading the word line WL is high, the state of bit lines of SRAM cells are substantially loaded. This is accomplished by the bit line driver input is designed to be relatively weaker than the transistor base unit more robust, so that the state of the bit line can substantially cover unit cross-coupled inverters previous state.
To write a cell is assumed, the first set to the high level BL, BL non-set low. After assert WL, so as to turn M5 and M6. After M5 and M6 is turned on, if the original storage cell 1, then the state does not change. If the original cell preservation 0, Q is low at this time, the cutoff Ml, M2 is turned on, Q is high, M4 is turned off, M3 turns on. Once assert WL is turned on such that M5 and M6, Q becomes high level (BL follow point level), thereby causing M1 is turned on, M2 is turned off. Once M1 is turned on, the high level of the original point Q will be discharged through M1, so that the point Q becomes low level. And in turn results in a low level of point Q M4 is turned on, M3 is turned off, so that locking point Q in the high level. The cell content of from 1 to a 0 is a similar process, not described in detail here.
Reference: HTTPS:? //Wenku.baidu.com/view/4938078b16fc700abb68fc89 fr = uc
http://www.wowotech.net/basic_subject/memory-hierarchy.html
