In the previous article, we learned about the basic structure and structure of on-chip SRAM. In this article, through some specific Memory Compiler, let’s get an in-depth understanding of the specific characteristics and different structures of SRAM. Let’s go!
For the design of an SRAM, in addition to the most basic core components (memory array), there are many components that need to be added in the components of the SRAM. With these necessary packages, the SRAM can provide a friendly environment for use. available to users.
Two structures: Register File vs. memory array
Conventional sequential logic does have a memory storage method. If a special layout method is used, it can simulate high-speed pipe-level access similar to register, and two read and one write operations can be completed in the same cycle (required here The internal read-write conflict control, resulting in read first and then write)
This structure is slightly different from the bit cell structure of the usual memory array, the benefit is that the cap value of the bitline and the memory array of the same size will have Decrease can effectively reduce the time to access the memory cell and improve the memory speed. But correspondingly, when the capacity of RF gradually expands, this method of reducing the cap through the structure will become less and less obvious, so the speed advantage of RF is only limited to small-capacity memory.
In the modern technology (60nm and below), RF is also built using bitcell, so from the point of view of bitcell, the basic period of RF and conventional memory array is the same size, this can be seen from the SRAM documentation of T family come out.
SRAM block diagram
An operationally controllable SRAM usually has rich interface controls, here is a simple T-family SRAM block diagram
It can be seen that the interface control pins here are far more than the control requirements of a simple memory array. The specific configuration of each pin is detailed in the table below
| pin | direction | describe | Classification |
|---|---|---|---|
| VDD | enter | Power supply for peripheral control devices | power ground |
| VDDM | enter | memory array power supply | power ground |
| VSS | enter | memory array and peripheral devices are grounded | power ground |
| A[*] | enter | address entry | Function |
| D[*] | enter | data input | Function |
| BWEB[*] | enter | bit write control | Function |
| CEB | enter | Chip Select | Function |
| WEB | enter | write control | Function |
| REDEMPTION | enter | Column Repair Redundancy Control | Function |
| Q[*] | output | memory array data output | Function |
| AVOID[*] | enter | Fail Bit Address Control | BIST test |
| DM[*] | enter | BIST data input | BIST test |
| AM[*] | enter | BIST address input | BIST test |
| BWEBM[*] | enter | BIST bit write control | BIST test |
| CEBM | enter | BIST Chip Select | BIST test |
| WEBM | enter | BIST write control | BIST test |
| ARE YOU | enter | BIST control | BIST test |
| DSLP | enter | Deep sleep mode: access to memory array is prohibited, but memory data will be saved | Low Power Control |
| SD | enter | Shut down: Shut down all memory arrays and most of the peripheral logic | Low Power Control |
| PUDELAY_SD | output | shutdown output flags to guide low power policy | low power consumption |
| PUDELAY_DSLP | output | deepsleep output flags to guide low power policy | low power consumption |
| DSLPLV | enter | Bypass control of retention diode in deepsleep mode | low power consumption |
| TSEL pin : WTSEL[ ]/RTSEL[ ] | enter | timing fine-tuning | test |
| TSEL pin : WTSEL[ ]/RTSEL[ ] | enter | timing fine-tuning | test |
| TSEL pin : WASEN | enter | write assist enable | test |
| TSEL pin : WASSEL[*] | enter | Write Assist Nudge | test |
In addition to common address, data, read and write and other functional categories, it can also be divided into the following categories according to the scene
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Power supply ground: Undoubtedly a must, but since the usual memory cells are very large, usually in the area of 100um * 100um, the connection of the power supply is more complicated than the two or three sentences described here. Mainly power requirements. In addition, VDDM and VDD do not need to be exactly the same, and can be distributed from different power sources, so that dual rail memory can be constructed to provide more low power consumption control possibilities.
It can be seen that the PG pins of the memory are very dense, mainly distributed in the middle part, which is also the place where the memory array, which consumes a lot of power, is concentrated -
BIST test: Built-in self-test, as the name suggests, this is a self-test and error mark for the physical storage characteristics of the memory. When encountering wrong data, you can use the internal bypass/mux method to transfer the correct data Read and write to other places. The BIST here is for memory and is usually called MBIST. All the pins related to BIST test can be controlled by MBIST logic to enforce memory.
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Test: TSEL pin is mainly used for fine-tuning the yield rate. After each batch of wafers is returned, machine testing is performed. Different batches of products may have slightly different performance, and it is reasonable to extract them through the test items. The adjusted value is stored in the efuse of the chip. After the chip is powered on, the content of the efuse can be read by the corresponding logic and micro-operations are performed on the memory to ensure the normal use of the chip. PS: This fine-tuning is very small, it is not recommended to adjust and use it in function mode
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Low power consumption: Based on the usage scenarios of memory, memory can be divided into shutdown, deep-sleep and normal modes. For example, the module at this level is a domain that can be turned off. Before turning off the std-cell logic, it is necessary to pull up (enable) the SD/DSLP of the memory to allow the memory to enter a different working mode to save power consumption. PS: If VDDM is powered off in DSLP mode, the contents of memory will be lost
SRAM redundancy repair (redundancy repair)
On a normal SARM, there may be a certain rate of bitcell failure. Based on different situations, it can be divided into column and row types of bitcell damage. For example, the bitcell of bit_i (column i) in the figure below is damaged. At this
time , all the data written to bit_i is shifted to the right in turn until bit_n-1 moves to the redun_1 column. At this time, redun_1 can be used to avoid the failure of the entire memory.
Correspondingly, row and column redundancy can be described using the following figure,
MBIST
MBIST is a way to test memory using BIST logic, which can locate the bad points of SRAM and repair it by calling the redundancy of column/row (usually also called MBISR: SRAM self-repair function). The testing method of MBIST is efficient, and it can be used in conjunction with the memory with redundancy bit to effectively improve the yield rate of the chip. The basic schematic diagram is as follows
step_1: In the ATE test environment, use MBIST logic to test each bit of the SRAM
step_2: Report the problem and classify the problem at the same time (repairable, unrepairable, whether repairable is usually based on the error Quantity and redundancy bit to determine)
step_3: If it can be repaired, in ATE mode, use the redundancy bit to repair the memory, if the MBIST test can pass at this time, then burn the relevant information into EFUSE.
Step_4: Enter user mode, start the chip, read the corresponding error memory ID and repair method from EFUSE. When using SRAM, the FADIO[*] input control will be clamped to the corresponding position to ensure that the SRAM can be used correctly.
For most of the memory, the MBIST channel is actually provided, as shown in the figure below:
However, considering the convenience of the back-end implementation, it is usually not used in this way. When using it, the MBIST pin is not generated, or directly tie0 drops. The simple connection method is as follows:
DFT testability
Since SRAM is composed of peripheral logic and memory array. The peripheral logic here is essentially some decoding logic built by std-cell. From the perspective of digital circuits, there is also the possibility of generating risks. Therefore, using the scan-chain DFT strategy can well analyze the testability of this part of the logic.
When the SRAM is in the DFT control mode, the test steps are as follows
step1: Use shift mode to configure the input port signal of the memory to a specified value
step2: Use capture mode to capture these port signals to the built-in scan-FF in the SRAM
Step3: Use the shift mode again. At this time, the memory array is in the bypass mode, and the value of scan-FF is shifted out in turn.
Step4: The observation results of DFT output pins such as SOC are compared with the input information of step1, and the SRAM peripheral is completed. Logical DFT test
Vocabulary in this chapter
| vocabulary | explain |
|---|---|
| MBIST | Memory Built-In Self Test (Memory Built-In Self Test) |
| MBISR | Memory Built-In Self-Repair (Memory Built-In Self-Repair) |
| Column Redundancy | SRAM Column Redundancy |
| Row Redundancy | SRAM row redundancy |
| DFT | Design For Test |
| ATE | Integrated Circuit Automatic Test (Automatic Test Equipment) |
[Knock on the blackboard to draw key points]
SRAM is composed of digital logic circuit (peripheral circuit) and storage unit (memory array), so it will show the characteristics of digital circuit (multi-VT legalize, scan chain, etc.) and the characteristics of storage unit (MBIST)
References
TSMC TSMC N7 SRAM Compiler Databook
TSMC TSMC N7 Design Rule