This example demonstrates the use of hardware and software:
- Chip Peripheral Driver Library: STM32CubeF41.24.1 of HAL library 1.7.6, April 12, 2019
- IDE: MDK-ARM 5.28.0.0, 2019 Nian 5 Yue
- Development Board: hanging off-chip SRAM 2 × FSMC_NORPSRAM3,16bit . 19 = 1MiB
Purpose of this example is to allow programmers to use as off-chip SRAM chip SRAM, like, i.e., without any of the variable declaration to the specified RAM address, the connector can be automatically put off-chip SRAM memory variables as
if all need to be declared off-chip SRAM variables into SRAM chip by __attribute __ ((at ()) ), and other indicators, then no need as in this example
Performing main () before executing the Flash chip, and the FSMC GPIO initialization instructions:
- Some instructions assembly code generated by the startup file, for example, the present embodiment is the startup file is STM32F407ZG startup_stm32f407xx.s (default version is STM32CubeF4 \ Drivers \ CMSIS \ Device \ ST \ STM32F4xx \ Source \ Templates \ arm)
- Some functions in system_stm32f4xx.c (located STM32CubeF4 \ Drivers \ CMSIS \ Device \ ST \ STM32F4xx \ Source \ Templates \)
For the present embodiment is STM32F407 modify the above two methods is the source file:
1. In other outer sheet SRAM for official use of memory to run a startup file routines
e.g. STM32CubeF4 \ Projects \ STM324xG_EVAL \ Examples \ FSMC \ FSMC_SRAM_DataMemory \ MDK-ARM \ startup_stm32f407xx.s
see adapted for use off-chip SRAM memory on local startup file compared to the version of the default startup files have changed
- Line 52, line 75: initializing the outer sheet defining a stack SRAM
- Line 191 Line 192 ~: before performing main (), after the stack pointer instruction after executing the boot file to the default values defined
52 __initial_spTop EQU 0x20000400 ; stack used for SystemInit & SystemInit_ExtMemCtl
75 __Vectors DCD __initial_spTop ; Top of Stack
191 LDR R0, =__initial_sp ; restore original stack pointer 192 MSR MSP, R0
2. Uncomment system_stm32f4xx.c line 96
91 /************************* Miscellaneous Configuration ************************/ 92 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ 93 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 94 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 95 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 96 /* #define DATA_IN_ExtSRAM */ 97 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ 98 STM32F412Zx || STM32F412Vx */
So the system_stm32f4xx.c
- 662, line 716 line to the
- Open GPIO clock module used in FSMC (line 662)
- Configure the GPIO port mode, speed information (the first line to the 667 line 712)
- Open FSMC clock module (line 716))
- Line 737 - line 741
- FSMC_NORPSRAM configuration control, the timing (the first line to the 739 line 741)
Will be executed
655 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 656 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 657 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 658 659 #if defined(DATA_IN_ExtSRAM) 660 /*-- GPIOs Configuration -----------------------------------------------------*/ 661 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 662 RCC->AHB1ENR |= 0x00000078; 663 /* Delay after an RCC peripheral clock enabling */ 664 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); 665 666 /* Connect PDx pins to FMC Alternate function */ 667 GPIOD->AFR[0] = 0x00CCC0CC; 668 GPIOD->AFR[1] = 0xCCCCCCCC; 669 /* Configure PDx pins in Alternate function mode */ 670 GPIOD->MODER = 0xAAAA0A8A; 671 /* Configure PDx pins speed to 100 MHz */ 672 GPIOD->OSPEEDR = 0xFFFF0FCF; 673 /* Configure PDx pins Output type to push-pull */ 674 GPIOD->OTYPER = 0x00000000; 675 /* No pull-up, pull-down for PDx pins */ 676 GPIOD->PUPDR = 0x00000000; 677 678 /* Connect PEx pins to FMC Alternate function */ 679 GPIOE->AFR[0] = 0xC00CC0CC; 680 GPIOE->AFR[1] = 0xCCCCCCCC; 681 /* Configure PEx pins in Alternate function mode */ 682 GPIOE->MODER = 0xAAAA828A; 683 /* Configure PEx pins speed to 100 MHz */ 684 GPIOE->OSPEEDR = 0xFFFFC3CF; 685 /* Configure PEx pins Output type to push-pull */ 686 GPIOE->OTYPER = 0x00000000; 687 /* No pull-up, pull-down for PEx pins */ 688 GPIOE->PUPDR = 0x00000000; 689 690 /* Connect PFx pins to FMC Alternate function */ 691 GPIOF->AFR[0] = 0x00CCCCCC; 692 GPIOF->AFR[1] = 0xCCCC0000; 693 /* Configure PFx pins in Alternate function mode */ 694 GPIOF->MODER = 0xAA000AAA; 695 /* Configure PFx pins speed to 100 MHz */ 696 GPIOF->OSPEEDR = 0xFF000FFF; 697 /* Configure PFx pins Output type to push-pull */ 698 GPIOF->OTYPER = 0x00000000; 699 /* No pull-up, pull-down for PFx pins */ 700 GPIOF->PUPDR = 0x00000000; 701 702 /* Connect PGx pins to FMC Alternate function */ 703 GPIOG->AFR[0] = 0x00CCCCCC; 704 GPIOG->AFR[1] = 0x000000C0; 705 /* Configure PGx pins in Alternate function mode */ 706 GPIOG->MODER = 0x00085AAA; 707 /* Configure PGx pins speed to 100 MHz */ 708 GPIOG->OSPEEDR = 0x000CAFFF; 709 /* Configure PGx pins Output type to push-pull */ 710 GPIOG->OTYPER = 0x00000000; 711 /* No pull-up, pull-down for PGx pins */ 712 GPIOG->PUPDR = 0x00000000; 713 714 /*-- FMC/FSMC Configuration --------------------------------------------------*/ 715 /* Enable the FMC/FSMC interface clock */ 716 RCC->AHB3ENR |= 0x00000001;
734 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ 735 || defined(STM32F412Zx) || defined(STM32F412Vx) 736 /* Delay after an RCC peripheral clock enabling */ 737 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); 738 /* Configure and enable Bank1_SRAM2 */ 739 FSMC_Bank1->BTCR[2] = 0x00001011; 740 FSMC_Bank1->BTCR[3] = 0x00000201; 741 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
Note from the 738 lines system_stm32f4xx.c seen, the first line to the 739 line 741 are arranged is FSMC_NORPSRAM2 control register read and write timing register, the register write timing, and off-chip SRAM development board hanging I use FSMC_NORPSRAM3 , it is necessary to modify the above-described write system_stm32f4xx.c GPIO registers, on FSMC code register, the register value for the correct method is nuclear opened only FSMC_NORPSRAM3 external peripherals and GPIO, and then copy the corresponding register value in the hardware debugging
3. Correct the above code system_stm32f4xx.c
( Once again reminded readers not read carefully question : The code below is only guaranteed to work with ((STM32F407ZG) && (off-chip SRAM hanging FSMC_NORPSRAM3) && (off-chip SRAM is 16bit × 219 = 1MiB)) case, and should be based on you use SRAM chips, AHB bus clock frequency information STM32 modified line to the 739th line 741 FSMC register configuration values used. spend a period mentioned method is suitable for obtaining the register value of your board, beginning with the article get the method mentioned in your microcontroller startup file):
655 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 656 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 657 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 658 659 #if defined(DATA_IN_ExtSRAM) 660 /*-- GPIOs Configuration -----------------------------------------------------*/ 661 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 662 RCC->AHB1ENR |= 0x00000078; 663 /* Delay after an RCC peripheral clock enabling */ 664 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); 665 666 /* Connect PDx pins to FMC Alternate function */ 667 GPIOD->AFR[0] = 0x00CC00CC; 668 GPIOD->AFR[1] = 0xCCCCCCCC; 669 /* Configure PDx pins in Alternate function mode */ 670 GPIOD->MODER = 0xAAAA0A0A; 671 /* Configure PDx pins speed to 100 MHz */ 672 GPIOD->OSPEEDR = 0xFFFF0F0F; 673 /* Configure PDx pins Output type to push-pull */ 674 GPIOD->OTYPER = 0x00000000; 675 /* No pull-up, pull-down for PDx pins */ 676 GPIOD->PUPDR = 0x00000000; 677 678 /* Connect PEx pins to FMC Alternate function */ 679 GPIOE->AFR[0] = 0xC00000CC; 680 GPIOE->AFR[1] = 0xCCCCCCCC; 681 /* Configure PEx pins in Alternate function mode */ 682 GPIOE->MODER = 0xAAAA800A; 683 /* Configure PEx pins speed to 100 MHz */ 684 GPIOE->OSPEEDR = 0xFFFFC00F; 685 /* Configure PEx pins Output type to push-pull */ 686 GPIOE->OTYPER = 0x00000000; 687 /* No pull-up, pull-down for PEx pins */ 688 GPIOE->PUPDR = 0x00000000; 689 690 /* Connect PFx pins to FMC Alternate function */ 691 GPIOF->AFR[0] = 0x00CCCCCC; 692 GPIOF->AFR[1] = 0xCCCC0000; 693 /* Configure PFx pins in Alternate function mode */ 694 GPIOF->MODER = 0xAA000AAA; 695 /* Configure PFx pins speed to 100 MHz */ 696 GPIOF->OSPEEDR = 0xFF000FFF; 697 /* Configure PFx pins Output type to push-pull */ 698 GPIOF->OTYPER = 0x00000000; 699 /* No pull-up, pull-down for PFx pins */ 700 GPIOF->PUPDR = 0x00000000; 701 702 /* Connect PGx pins to FMC Alternate function */ 703 GPIOG->AFR[0] = 0x00CCCCCC; 704 GPIOG->AFR[1] = 0x00000C00; 705 /* Configure PGx pins in Alternate function mode */ 706 GPIOG->MODER = 0x00200AAA; 707 /* Configure PGx pins speed to 100 MHz */ 708 GPIOG->OSPEEDR = 0x00300FFF; 709 /* Configure PGx pins Output type to push-pull */ 710 GPIOG->OTYPER = 0x00000000; 711 /* No pull-up, pull-down for PGx pins */ 712 GPIOG->PUPDR = 0x00000000; 713 714 /*-- FMC/FSMC Configuration --------------------------------------------------*/ 715 /* Enable the FMC/FSMC interface clock */ 716 RCC->AHB3ENR |= 0x00000001;
734 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ 735 || defined(STM32F412Zx) || defined(STM32F412Vx) 736 /* Delay after an RCC peripheral clock enabling */ 737 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); 738 /* Configure and enable Bank1_SRAM2 */ 739 FSMC_Bank1->BTCR[4] = 0x00001091; 740 FSMC_Bank1->BTCR[5] = 0x0FFFFFFF;
4. In the MDK-mapped address range FSMC_NORPSRAM3 1M 0x68000000 ~ 0x6BFFFFFF first set of memory operation
At the lower right corner of FIG. 0x68000000,0x100000 are filled window "Read / Write Memory Areas" to "off-chip" is any line:
5. After modification Reuild
(Note: MDK-ARM may not know which files are modified by the user, so if only the Build, the IDE may then take the old object files compiled version of the source file to get the connection)
Can be seen from the MAP file, a variable is assigned to the off-chip SRAM address range 0x68000000 ~ 0x68100000 map, and the normal microcontroller program
Exec Addr Load Addr Size Type Attr Idx E Section Name Object 0x68000000 0x0800628c 0x00000008 Data RW 19 .data main.o 0x68000008 0x08006294 0x00000008 Data RW 247 .data stm32f4xx_hal_msp.o 0x68000010 0x0800629c 0x0000000c Data RW 1539 .data stm32f4xx_hal.o 0x6800001c 0x080062a8 0x00000004 Data RW 1772 .data system_stm32f4xx.o 0x68000020 0x080062ac 0x00000004 Data RW 1842 .data tftlcd.o 0x68000024 - 0x00000050 Zero RW 18 .bss main.o 0x68000074 - 0x0000000e Zero RW 1840 .bss tftlcd.o 0x68000082 0x080062b0 0x00000006 PAD 0x68000088 - 0x00000400 Zero RW 1 STACK startup_stm32f407xx.o
CubeMX desired future versions will be automatically set to the off-chip RAM memory on