Reproduced label: shamedram |
Category: Work Package |
SRAM works:
In a static memory device, one of six transistors, referred to as a memory storage element, as shown in FIG:
Nl and N2 constitute a flip-flop, P1, and P2, respectively, as a load resistance Q1 and Q2. N1 OFF state when N2 is turned on and referred to as "a." The opposite condition is called "0."
When read, select line is set to a high level, so that the two switches is turned on, from the read / write line output of the original deposit.
When writing, data is written so that the read / write line was a corresponding level (e.g., writing "1", the read / write line "1" is high, the read / write line "0" is low), then the selection line is high, then the flip-flop is set to a corresponding state (write "1" is set to "1" state, i.e. N1 N2 is turned off). Clearly, whether the meta information stored in the memory is "1" or "0", N1, N2, P1 and P2,4 only two MOS transistors are always in a conducting state.
DRAM works
And as static RAM, dynamic RAM is substantially composed of many memory elements in rows and columns thereof.
(1) 3 of the DRAM three basic dynamic RAM memory circuit as shown on the right. In this circuit, the read and write selection line selecting lines are separated, the read data lines and write data lines are separate. When a write operation, the write select line is "1", so that Q1 is turned on, the data to be written to the gate through Q1 and Q2, and the information held by the gate capacitance within a certain time. When a read operation, the first by a common pre-charge transistor Q4 so that the read data line distributed capacitance CD is charged, when the read selection line is active high, Q3 is in a conducting state. If there had "1", Q2 is turned on, the read data line distributed capacitance CD through Q3, Q2 discharge by the read information is "0", and exactly opposite to the original information stored; if the original stored information is "0 "Although the conditions have Q3 is turned on, but because Q2 is turned off so that the voltage on the CD remains unchanged, and thus, the read information is" 1. " Seen, such a memory circuit, read the information stored in the original and the opposite, so is inverted by a sense amplifier and then sent to the data bus.
(2) single tube DRAM
① First, a positive write pulse signal T5 is turned on so ф balance trigger, then the tube T5 is turned off, row, column strobe signal active high, T6, T0 is turned two, if I / O data line input logic 0 level, the tube T1 is turned off, the inverter T1, T3 constituted by places high C T0 stored in the capacitor C is charged. Conversely, if the I / O input line to a logic one level as input, after T1 inverted to a logic zero level C is stored, if the original C in a charge, it will form a discharge circuit, exhausting the capacitance C stored charge. C is stored in the result of these analyzes, the memory cell circuit inverting the input logic signal
identical conditions ② start the read operation and write operation, this time T6, T0 two turned on if the charge in the capacitor C i.e. is high, after the transfer tube to the gates T0 and T2, the T2 drain output a low level is stored previously, this can in turn cause low reliability T1 is turned off, then T1, T3 inverting composition outputs a high level via standard charges C T0 and thus, achieve both the read operation read out correctly, but also to achieve regeneration (refresh)
③ refresh operation refresh operation is also known regeneration operation. Refresh generally achieve a "RAS-only valid" refresh method, this time, the column address is inactive DRAM selected by the row address valid in a row, the row of binary information stored in a read operation to achieve all this, from the read operation foregoing, the read operation may be achieved while achieving regeneration read. Because the column address is invalid, read access to all of the binary information and is not output to external I / O data lines to