Now we generally know that the general conversion process of ADC is to input an analog signal, and finally convert it into a digital signal through sampling, holding, quantization, encoding and other processes. Next, we will use the ADC module block diagram to understand what the ADC module needs to do for normal operation.
Preparation Phase:
- Configure the frequency division number (control ADC cycle)
- ADC input range control (the input signal needs to be within the ADC conversion range)
- ADC sampling time
- ADC input method (rule group/injection group)
- ADC working mode (single/continuous, scan or not)
ADC conversion: the point in time when the conversion starts
ADC conversion completed: Whether to enable the interrupt of conversion completion (interrupts corresponding to different input methods are different)
1. What is ADC?
1. Basic concepts of ADC
ADC (Analogto-Digital Converter ) is a peripheral that converts analog signals into digital signals. The temperature values and voltage values we are familiar with are actually analog signals, but the microcontroller only recognizes high and low levels. If we want the microcontroller to process these analog signals, we need to convert the analog signals into digital signals through the ADC.
2. ADC resolution
We usually always say "12-bit AD sampling", which means that the current AD value ranges from 0 to 2^12-1, that is, 0 to 4095. If the input voltage is 0~3.3V, it is equivalent to dividing 3.3 V into 4096 equal parts; if it is 16-bit AD sampling, it is equivalent to dividing 3.3V into 65536 equal parts.
Resolution emphasizes precision. The more copies, the finer the granularity, and the more accurate the conversion result will be.
2. ADC implementation block diagram
The following is the structure diagram of the ADC module. For ease of understanding, it is roughly divided into seven parts. Please read in counterclockwise order from the left.
① Voltage input range
In order to improve the accuracy of conversion, the ADC uses an independent power supply to filter and shield the glitch interference from the printed circuit board. The power supply pin of the ADC is VDDA and the independent power supply ground VSSA.
Vref+ and Vref- represent the voltage range that the ADC can convert, that is, the voltage range that the ADC can measure is Vref- ≤ Vin ≤ Vref+. (Internal Vref+ is connected to VDDA, Vref- is connected to VSSA)
② Analog signal sampling (sampling time)
ADCx_IN0 ~ 17 are the input channels of ADCx, and each channel can be connected to an analog signal input source. Before inputting the analog signal to the channel, you need to perform a " sample and hold " operation on the analog signal. The time spent in this step is the " sampling time ", which is also a necessary configuration item for our subsequent program. ( For the reasons for sampling and holding, please refer to the last module of the article )
Which IO pin a certain channel of ADCx is connected to is decided in advance. The following is the channel-pin correspondence of the stm32f4 series. For example, the IO pin connected to channel 0 of ADC1 is PA0. Channels 16 ~ 18 are special. Channel 16 is connected to the temperature sensor inside the chip, channel 17 is connected to the internal reference voltage Vrefint, and channel 18 is the backup power pin Vbat.
③ Ways to trigger AD conversion (software/hardware)
The methods of triggering AD conversion include software trigger and hardware trigger. The software trigger is to start conversion by writing 1 to the AD ON bit of the ADC-CR2 register; the hardware trigger can be a timer (TIM) trigger or an external pin (EXIT) trigger.
There are two sets of triggers on the left and right in the picture, which are related to the input method of AD. The left side is dedicated to the injection group, and the right side is dedicated to the rule group.
④ ADC frequency division (ADC cycle)
The clock frequency division determines the ADC cycle, which requires reference to the clock tree. The ADC clock comes from the APB2 bus. Divide the APB2 bus clock again to get the ADC clock frequency. The frequency division number can be 2/4/6/8.
As can be seen from the clock tree, we can divide 180MHz by 1 / 2 / 4 / 8 / 16. The divided clock frequency is the clock frequency of the APB2 bus. Different peripherals on the APB2 bus have different clock requirements. It is impossible for every peripheral to use the same clock frequency, so it needs to be divided again before providing it to the ADC.
⑤ Input method
ADC has two input methods, namely injected channels and regular channels. It is equivalent to sending a conversion list to the AD converter and telling him which channels to convert.
Injection group:
Up to 4 channels can be converted at one time, and the conversion results are saved to the injection group data register (the injection group has 4 data registers, each register is 16 bits in length)
Rule group:
Up to 16 channels can be converted at one time, and the conversion results are saved to the rule group data register (the rule group has only 1 data register, and the length of each register is 16 bits). The rule group is best used with DMA . The rule group has only one register. Once the upper layer does not retrieve the conversion result in the register in time, the result in the register will be overwritten by the next result .
⑥ Working method
The working method of ADC is mainly reflected in the quantization encoding stage. We may have to consider two issues:
- After starting the conversion, although multiple channels will be input, is it converted one at a time or a group? (non-scan/scan)
- After the conversion is completed, should you stop here or continue the conversion? (Single/Continuous)
Assume that the input method is injection group.
Non-scan/scan mode
Non-scan: No matter how many inputs are entered, only the first one is converted. For example, three channels are input below, but only the 0th position, which is channel 0, will be converted in the end.
Scan: What you input is converted.
Single/continuous conversion
Single conversion: Stop after converting once, and the conversion will not start until restarting next time
Continuous conversion: After one conversion, continue to start the next conversion
⑦ Flag bit, interrupt enable
When the conversion is completed, the corresponding flag bit will be automatically set to 1, and we can enable the interrupt to notify.
- OVR : The conversion result is completed using DMA transfer
- EOC : Injection group/rule group conversion completed
- JEOC : Injection group conversion completed
- AWD : Trigger watchdog event (need to set the water level, when it is higher or lower than a certain water level, the event will be triggered)
3. Why is "sample and hold" needed?
Analog signals are continuously input, that is, they are changing. We hope that when converting analog signals, the analog signals will be fixed. Therefore, you need to use sample and hold (the sample and hold circuit is used to achieve this purpose)
During the sampling phase, the switch S is closed, the capacitor CH is charged, and the output voltage Vo changes with the analog signal.
In the holding phase, the switch S is turned off, the capacitor CH is discharged, and the output voltage Vo remains at the input signal value at the moment when the analog switch is turned off.
The time from switch S closing to switch S opening is the so-called "sampling time". If the sampling time is too long, it will affect the overall AD conversion time; if the sampling time is too short, it will easily lead to insufficient charging time for the capacitor, and the collected voltage value will be lower than the actual voltage value.
4. ADC conversion time calculation
After the sampling is completed, it is equivalent to preparing the data. Next, the analog signal must be converted into a digital signal (binary encoding) through the "quantization encoding" stage.
It can be seen that conversion time = sampling time + quantization encoding time. The quantization encoding is generally 12.5 ADC cycles. therefore,
Conversion time = sampling time + 12.5 ADC cycles
The maximum ADC clock frequency is 14MHz, assuming the sampling time is 1.5 cycles, then
Conversion time = 1.5 + 12.5 = 14 ADC cycles = 1us
Reference article:
STM32 study notes - Frequently asked questions about ADC data collection - Zhihu (zhihu.com)
Detailed explanation of ADC in STM32-Electronic Enthusiasts Network (elecfans.com)