3.Simple wire
problem:Create a module with one input and one output that behaves like a wire.
module top_module( input in, output out );
assign out = in;
endmodule
4.Four wires
problem:Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:
a -> w
b -> x
b -> y
c -> z
module top_module(
input a,b,c,
output w,x,y,z );
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
5.inverter | Notgate
problem:Create a module that implements a NOT gate.
module top_module( input in, output out );
assign out = ~in;
endmodule
6. And gate
problem:Create a module that implements an AND gate.
module top_module(
input a,
input b,
output out );
assign out = a & b;
endmodule
7.Nor gate
problem:Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.
module top_module(
input a,
input b,
output out );
assign out = ~(a | b);
endmodule
8.Xnorgate
problem: Create a module that implements an XNOR gate.
module top_module(
input a,
input b,
output out );
assign out = ~(a ^ b);
endmodule