HDLBits_Verilog Language_Basics心得总结

Wire

Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog “continuous assignment” (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is “continuous” because the assignment continues all the time even if the right side’s value changes. A continuous assignment is not a one-time event.

As you might expect, a wire cannot have more than one driver (what is its logic level if there is?), and a wire that has no drivers will have an undefined value (often treated as 0 when synthesizing hardware).

心得

assign为连续赋值，相当于将两个wire连接，其中等式右边为driver，等式左边为sink，不能将同一信号连到两条线上，即不能有两个driver。

Wire4

When you have multiple assign statements, the order in which they appear in the code does not matter. Unlike a programming language, assign statements (“continuous assignments”) describe connections between things, not the action of copying a value from one thing to another.

心得

当存在多个assign语句时，assign出现的顺序和位置不影响，结合上面的理解，相当于连线的顺序不影响最终结果，这个要和软件的思维区别开。

Basic gates

separate bitwise-NOT(~) and logical-NOT(!)

separate bitwise-AND(&) and logical-AND(&&)

separate bitwise-OR(|) and logical-OR(||)

A NOR gate is an OR gate with its output inverted.

bitwise-XOR

7458 chip

Solution1：

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
        wire and1_out,and2_out,and3_out,and4_out;
        assign and1_out=p2a&p2b;
        assign and2_out=p2c&p2d;
        assign and3_out=p1a&p1c&p1b;
        assign and4_out=p1f&p1e&p1d;
        assign p2y=and1_out|and2_out;
        assign p1y=and3_out|and4_out;
endmodule

Soluton2：

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p2y=(p2a&p2b)|(p2c&p2d);
    assign p1y=(p1a&p1c&p1b)|(p1f&p1e&p1d);
endmodule

总结

1、assign为连续赋值，赋值顺序不影响。

2、一个wire有且仅能有一个driver。

3、学习了Basic gates。

HDLBits心得总结(1)_Verilog Language_Basics