HDLBits-Verilog学习记录 | Getting Started

1.Getting Started

problem: Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

答案不唯一，仅供参考：

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

相关解释：
top_module顶层模块不可修改

2.Output Zero

problem: Build a circuit with no inputs and one output that outputs a constant 0
答案不唯一，仅共参考：

module top_module(
    output zero
);// Module body starts after semicolon
	assign zero = 0;
endmodule

相关解释：这里挺类似于c语言的语法风格