The Altera Cyclone IV device having a PLL clock multiplication and division, phase offset, programmable duty cycle output and the external clock, the clock management system-level control and offset. Altera's Quartus II software does not require any external device, you can enable Cyclone IV PLL and related functions.
The following demonstrates the nuclear and call ALTPLL Altera provided to generate a clock of a different frequency, and the external clock to the FPGA IO:
1, the establishment of the project (see above a specific blog)
2, then open the IP generation wizard, select menu Tools-> MegaWizard Plug-In Manager.
3, in the first page of the wizard interface IP default choice Create a new custom megafunction variaion, and then click Next.
4. Select ALTPLL under the I / O directory in the second page of the IP list IP wizard interface, and then in the "What name doyou want for the output file?" Bar, enter the directory name and IP storage, IP name here we named pll.
5, modify the configuration of the PLL in ALTPLL Page3 interface where input clock 50Mhz, because we use the development board of the clock is 50Mhz. In addition, there are four PLL operating mode, here we choose the default In normal mode.
. 6, Page3 interface select the default input and output signals can be.
7, keep the default just fine.
8, configuration Page6 select the input always inclk1, we do not have here, keep the default settings, click the Next button.
9, PAGE7 choose dynamic configuration of the PLL output, to achieve real-time online configuration, if we PLL output frequency is fixed and does not need to choose.
10, selecting the output frequency c0 in the configuration of the interface 8, the output frequency where we manually enter c0 is 25Mhz. M and N software automatically calculates the VCO.
11, clk c1, c2, c3, c4 all uncheck use this clock, only the output all the way here. Then click finish;
12, the software prompts to add IP file to the project, we click on the Yes button.
13, in the File interface, we can see the generated pll.qip and pll.v files have been added to the project.
14, design a verilog file to instantiate the PLL IP, verilog code written as follows.
15, save, and the set top layer module;
16, configuration pins, the Compile Design compile the project, you can download.