EDITORIAL words
Dream Wings brothers often tell you , the most obvious advantage is its speed FPGA. Then this section, we dream wings together brothers and clock management unit FPGA chip PLL (Phase Locked Loop) is applied learning. The use of phase-locked loop, we can implement any in a very broad range of frequency division and multiplication. The use of phase-locked loop, can effectively reduce the amount of code we had a part of the clock, and more importantly, the use of phase-locked loop of "global clock tree", the clock can guarantee good quality.
Project requirements
We use two phase-locked loop generates a clock, all the way to 25MHz, another way to 100MHz. In this way we can learn to use phase-locked loop to achieve the basic operations of the division and multiplication.
Steps
Start Quartus15.0 
on the right side of the interface type pll IP Catalog search, and then double-click [] ALTPLL
Select the language for Verilog, give IP a name, call it here my_pll
Click [ ok ] in the future, the interface will enter pll setup wizard, type our input clock frequency (crystal or external clock), then click [ NEXT ]
We [areset] and [locked] tick ( areset: PLL high-level reset signal. Locked : When the PLL output stable, locked becomes a high level ), and then click [NEXT]
Continue to click [ NEXT ] until the following interface
Select [ Enter output clock freqquency ] type of output clock frequency we want, then click NEXT
Choose to use the second clock, the clock frequency of the type we want.
Continue to click [ NEXT ] until the following screen appears, then select my_pll_inst.v (this document is to call IP core port), click [ Finish ]
Top-level architecture design
In the ip-core setup wizard, we learned about the port's phase-locked loop, draw architecture diagram below:
Port Description
| Port Name |
Port Description |
| clk |
The input clock |
| areset |
Active high Reset |
| Clk_25M |
25MHz clock output |
| Clk_100M |
100MHz clock output |
| locked |
Stable clock signal |
Code explanation
Call the phase-locked loop module code:
| /**************************************************** * Engineer: Dream Brother Wing * QQ : 761664056 * The module function: PLL application *****************************************************/ 01 module pll ( CLK 02 , // input clock Areset 03 , // reset signal Clk_25M 04 , // 25M clock output Clk_100M 05 , // 100M clock output 06 locked // clock signal stability 07 ); 08 // system input 09 INPUT CLK ; // input clock 10 INPUT the areset ; // reset signal 11 // system output 12 is Output clk_25M ; // 25M clock output 13 is Output clk_100M ; // 100M clock output 14 output locked; //时钟稳定信号 15 // 调用IP核 16 my_pll my_pll_inst ( 17 .areset ( areset ), //复位信号 18 .inclk0 ( clk ), //系统时钟输入 19 .c0 ( clk_100M ), //100M的时钟输出 20 .c1 ( clk_25M ), //25M的时钟输出 21 .locked ( locked ) //时钟稳定信号 22 ); 23 24 endmodule |
本模块中只是简单的调用了pll的IP核，主要目的是让大家学会如何调用IP核。
仿真代码如下：
| /**************************************************** * Engineer : 梦翼师兄 * QQ : 761664056 * The module function: 锁相环模块的测试 *****************************************************/ 01 `timescale 1ns/1ps //时间单位和精度定义 02 03 module pll_tb; 04 05 //系统输入 06 reg clk; //输入时钟 07 reg areset; //复位信号 08 //系统输出 09 wire clk_25M; //25M的时钟输出 10 wire clk_100M; //100M的时钟输出 11 wire locked; //时钟稳定信号 12 13 initial begin 14 clk = 1; 15 areset = 0; 16 end 17 18 always # 10 clk = ~clk; //50MHz时钟 19 20 pll pll( 21 .clk(clk), //输入时钟 22 .areset(areset), //复位信号 23 .clk_25M(clk_25M), //25M的时钟输出 24 .clk_100M(clk_100M), //100M的时钟输出 25 .locked(locked) //时钟稳定信号 26 ); 27 28 29 endmodule |
仿真结果分析
当输出的时钟稳定之后，locked（时钟稳定信号）信号由低变高。输出的两路时钟中，一路为20MHz，一路为100MHz，与我们的设计要求一样，证明我们的操作和代码都是正确的。