First, the independent watchdog function
Regular view the situation inside the chip, once the error has occurred on the issue of restarting signal to the chip. Watchdog command has the highest priority interrupt program.
Second, the start of an independent watchdog STM32 step
①, 0X5555 to IWDG_KR write register. And for canceling the write protection IWDG_PR IWDG_RLR, so that the rear can be operated both registers.
IWDG_PR IWDG_RLR set value and the set value of the division factor and reload the watchdog.
DOG watchdog time calculation: Tout = ((4 × 2 ^ prer) × rlr) / 40
Wherein Tout is a watchdog time (in ms); prer watchdog clock prescaler value (IWDG_PR value), the range of 0 ~ 7; rlr watchdog reload the value (value of IWDG_RLR); For example, we set the value prer 4, rlr value 625, then it can be obtained Tout = 64 × 625/40 = 1000ms, such the watchdog time is 1s, as long as you are within one second, once written 0XAAAA to IWDG_KR, will not lead to a watchdog reset (of course also possible to write many times).
It should remind everyone that the watchdog's clock is not accurate 40Khz, so when feed the dog, it is best not too late, otherwise, it may happen watchdog reset.
② write 0XAAAA to IWDG_KR.
By the phrase, STM32 will reload the watchdog counter to the value IWDG_RLR inside. I.e. independence watchdog operation feed the dog.
③ the write 0XCCCC IWDG_KR.
By the phrase to start STM32 watchdog. Note IWDG at Once enabled, it can not be turned off! I want to turn off, restart only, and can not be opened IWDG after the restart, otherwise the problem remains.
So here remind, if not IWDG, then, is not going to open it, lest trouble.
Third, software design
wdg.c
#include " wdg.h " // initialize independent watchdog @ PreR: frequency division number: (! only the lower 3 bits) 0 ~ 7 @ frequency division factor = 4 * 2 ^ prer but only a maximum value. is 256! @ RLR: reload register values: lower 11 bits are valid. // time calculation (approximate): Tout = ((2 * ^ PreR. 4) * RLR) / 40 (MS). void IWDG_Init (U8 PreR, u16 rlr) { The IWDG -> KR = 0x5555 ; // enable write to IWDG-> PR and IWDG-> RLR of IWDG-> PR = PreR; // set the frequency division factor IWDG-> RLR = RLR; // loaded from register IWDG- > RLR, IWDG-> KR = 0xAAAA ; // reload IWDG-> KR = 0XCCCC ; // enable watchdog } // Hey independent watchdog void IWDG_Feed ( void ) { IWDG->KR=0XAAAA;//reload }
wdg.h
#ifndef __WDG_H #define __WDG_H #include "sys.h" void IWDG_Init(u8 prer,u16 rlr); void IWDG_Feed(void); #endif
The main function
int main(void) { Stm32_Clock_Init ( . 9 ); // system clock delay_init ( 72 ); // delayed initialization uart_init ( 72 , 9600 ); // serial port initialization LED_Init (); // hardware interface initialization connected to the LED KEY_Init (); // initialization key Delay_ms ( 300 ); // let off visible IWDG_Init ( . 4 , 625 ); // with the division number is 64, 625 is overloaded, overflow time lS LED0 = 0 ; // lighting LED0 the while ( 1 ) { IF (KEY_Scan ( 0 ) == WKUP_PRES) IWDG_Feed (); // if WK_UP pressed, the dogs Delay_ms ( 10 ); }; }