Overview
The independent watchdog is used to monitor the operation of the system. If the CPU runs abnormally and cannot be cleared regularly, the watchdog will generate a global reset signal after overflow to
restart the system to avoid system lockup. The watchdog starts automatically after the chip is powered on and cannot be turned off; in order to facilitate debugging,
when the chip is in the debugging mode, the software can suspend the IWDT during the debugging process by configuring the MCUDBGCR register.
The independent watchdog uses LSCLK to work, and the overflow period can be configured as 125ms, 500ms, 2s, 8s, 4096s, and the 4096s gear
can only be used in sleep mode. Once the chip wakes up from sleep mode, it will automatically switch back to one of the 4 normal cycles, and
after the wake-up is completed, the hardware will automatically clear the dog and start counting again.
IWDT operation
When the CPU is running normally, the watchdog should use a short overflow period. In low-power modes such as SLEEP/DEEPSLEEP, in order to
keep the chip in low-power mode for as long as possible, the watchdog A longer overflow period should be used.
In order to be compatible with the different application requirements of the two, the software can modify the overflow period configuration of the IWDT in real time. In order to avoid unpredictable
consequences caused by improper operation, the software should follow the following steps when updating the overflow cycle configuration:
➢ Make sure the watchdog is running
➢ First perform a dog clearing operation
➢ Then rewrite the IWDTCFG register to select a suitable overflow cycle
➢ Read IWDTCFG to make sure the writing is correct
. ➢ The overflow cycle is updated and the CPU runs normally.
In RTCBKP mode, the IWDT stops running.