Constitute an embedded system
Software:
Application
third-party libraries (Qt, libc, myclient)
operating system:
boot loader
kernel + drivers
file system
hardware:
floor:
an external chip
card (DM9000)
sound card
ADC
Power
USB
Interface:
Serial
SD
the LCD + touch screen
camera
button
core board:
Soc (the CPU + + the Timer UART)
DDR
Nand
ARM architecture
A, ARM mode of operation
User mode
system mode
fast interrupt mode
external interrupt mode
privileged mode
Quick mode
an undefined mode
in addition to user mode, privileged mode is referred to other
user mode and the system mode, the other mode is called an exception
Two, ARM register
A total of 37 registers, the user can use the mode and the system mode 17, other modes can be used (17+ backup status register) 18.
r0 ~ r7: all common mode
r8 ~ r12: the fast interrupt mode has its private, other common mode.
r13 ~ r14: common user mode and the system mode, other modes are private.
r15, cpsr: all common mode
r15 also known as pc: program counter, it records the next program to be executed, can be assigned, thus achieving a jump.
cpsr: recording user on an instruction execution state, carry, overflow, zero, negative, the current mode, only 12-bit effective, other bits are currently reserved.
spsr: the user mode and the system mode is not, there are other modes of private.
Like cpsr format, which is used to back up the user mode and the system mode cpsr.
Third, the pipeline
An instruction execution requires six steps of:
a fetch
2, decoder
3, fetch
4 calculates
5, a memory
6, a write back
if only performed sequentially, then performing one of the operations of the other hardware are idle , ARM has introduced the concept of assembly line, each control unit is only responsible for doing one thing, so in theory, three-stage pipeline would be increased to three times the performance, while the 5-stage pipeline would be increased five times the performance.
But the reality is in fact reach, because the pipeline will be interrupted, suspended.
For example:
BL FUNC // jump instruction
LDR r0 of, [r0 of, # 0]
the Add r0 of, r0 of, R1 // generated on the five-stage pipeline
Four, ARM processor addressing
1. Addressing now: 100 #
2 register addressing: r0, when the register variables
3. Register indirect addressing: [r0], the register when the pointer variables, * r0 of
4. Offset Register Addressing: r0 of << n, the register is left or right operation
5. based indexed addressing: [r0, # 1], corresponding to subtraction operation pointer variables, * (r0 of +. 1);
6. The multi-register addressing: register batch operation, the initializing operation is similar to the array
7. stack addressing: the statement may also be used in the stack memory and heap memory ARM assembler, but only to set the base address of the stack memory and heap memory is good, and then It can be read to the memory heap and stack data is written.
Five, ARM instruction set
1, the ARM instruction format
<of opcode> {<cond>} {S} <Rd>, <Rn> <Operand2> ...
of opcode instruction code
cond condition code
S affect the status register
Rd destination register
Rn source register
{may} omitted and <> must be a
2, RM and the instruction execution conditions flag
CMP comparison result is automatically stored in the status register
and the data processing instructions necessary to add anti-S will command the calculated result stored into the status register.
EQ equal
NE unequal
3, branch instruction
B target address is a relative address jump, adding an offset value based on the current address, jump, jump speed which is faster, but jump limited range, plus or minus 32M.
BL destination address is an absolute address of the branch, a complete address is required before the jump will store the address of the next instruction into r14, execution then jumps to the target location, when the execution is completed, from r14 are restored to the pc, thus achieving a return.
BL and BLX similar function, but from the ARM (32-bit status), switching to the Thumb (16-bit status).
BX function is similar to B, but from the ARM (32-bit status), switching to the Thumb (16-bit status).
4, the data processing instruction
MOV r0 of, # 100 = 100 <=> r0 of
MOV Rl, R3, LSL, #. 3 <=> = R3 << R1. 3
MVN r0 of, # = 100 ~ 100 <=> r0 of
the ADD r0 of, R1 , # 110 + 110 <=> R1 = r0 of
the SUB R0, R0, # = R0-. 1. 1 <=> anti Save
the RSB R3, Rl, R3 # = 0xFF00 <=>-R1 0xff00
the ADDS Rl, Rl, R2
the ADC R0 , R0, R2 plus carry bit
SUBS R0, R0, R2
the SBC Rl, Rl, R3 subtract with carry
R2 RSBS, R0, # 0
the RSC R3, Rl, # 0 of the anti-reflection with borrow
R0 the AND, R0, #. 3. 3 & r0 of <=> = r0 of
the ORR R0, R0, #. 3 <=> = r0 of r0 of |. 3
the EOR Rl, Rl, R1 = R1 <=>. 3 # ^. 3
BIC R0, R0, #. 3 = r0 of r0 of & <=> (~. 3)
the CMP Rl, the comparison of two numbers R0 influence the status register
CMN R1, R0 after comparing the two numbers negated, and the results of the comparison result influence the status register
TST R0, # 0x01 the two numbers bitwise aND operation and the calculation result affect the status register
TEQ R1, R2 two numbers bitwise XOR operation, and the calculation result affect the status register
5, the program status register transfer instruction
MRS R7, CPSR the backup status for the current mode to R7
the MSR CPSR_cxsf, the data is written into the status register R3
[31:24] of the condition flag field, represented by f
[23:16] of the status bit field, represented by s
[15: 8] is an extension bit field, represented by x
[7: 0] of the control bit field, and c represents
6, load, Store instruction
load from memory data is loaded into the register
the LDR R0, # 8
the LDR R0, [Rl, # 8] * = r0 of <=> (R1 +. 8);
DMFD R13, {R0, R4-R12, the LR}
Store the data register to the memory
STR # 8, R0
R0 the STR, [Rl, #. 8] * (R1 +. 8) = r0 of
STMFD R13, {R0, R4-R12, the LR}
the SWP r0 of, R1, R2 = r0 of <=> R2; R2 = R1;
. 7, interrupt instruction
SWI 0-16777215 Once this directive will enter break mode.
Sixth, Power Lock:
1, find the code provided by the manufacturer, start.S saved as a file.
Start:
LDR r0 of, 0xe010e81c =
LDR R1, [r0 of]
ORR R1, R1, # 0x300
ORR R1, R1, # 0x1
STR R1, [r0 of]
2, generate object code
arm-none-linux-gnueabi- gcc -c start .S -> start.o
. 3, executable file (setting code segment, the boot code is not added, without addition of standard library)
ARM-none-Linux-GCC-gnueabi -Ttext 0xd0020010 -nostartfiles -nostdlib start.o -o Lock
4, copy the executable file from a pure binary instructions
ARM-none-Linux-gnueabi-objcopy -O binary Lock lock.bin
5, check and compile tools added (look, tomorrow we wrote a)
gcc -o mkv210 mkv210_image.c
. 6, to add a checksum lock.bin
./mkv210 lock.bin lock_image.bin
. 7, the checksum is added and after programming files to the SD card executed, effects: development board can continue to supply .