ARM Overview and basic programming model
ARM processor mode
User mode (User, usr)
Fast interrupt mode (FIQ, fig)
External interrupt mode (IRQ, irq)
Privileged mode (Supervisor, sve)
Data Access suspend mode (Abort, abt)
Undefined instruction pause mode (Undefined, und)
System mode (System, sys)
The other six outer processor mode called user mode privileged mode. Among these, in addition to the system mode, among other five modes, other 5 abnormal pattern called a privilege mode.
ARM register
ARM processor has 37 registers, comprising:
31 general-purpose registers, including the program counter (PC) included. Are 32
6 status registers. 32, except that 12 wherein
ARM processor seven different processor modes, each mode having a corresponding set of registers.
At any time, visible registers include 15 general purpose registers (R0 ~ R14), one or two status registers and a program counter (PC).
General-purpose registers
Divided into three categories:
Not backed up registers, R0 ~ R7 comprises
Backup registers, including R8 ~ R14
The program counter PC, that is R15
Program Status Register
The CPSR (Current Program Status Register): can be accessed in any processor mode, comprising condition flags, interrupt disable bits, the current processor mode flag and other control and status bits.
The SPSR (backup program Status Register): When a specific exception interrupt occurs, this register contains the current contents of the register. When abort the program exits, it can be saved to restore the value of CPSR with the SPSR.
Since the user mode and system mode is not abort mode, so they do not SPSR. When the result to access the SPSR in user mode and system mode, will produce unpredictable
| 31 | 30 | 29 | 28 | 27 | 26 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| N | WITH | C | V | Q | DNM (RAZ) | I | F | T | M4 | M3 | M2 | M1 | M0 |
N: = 1 indicates negative
Z: = 1 the result is 0
C: up and down overflow
V: the sign bit overflow
I, F, T, and M [4: 0]: the control bits, I, F is a disable bit, IRQ, FIQ. Description This instruction is a T ARM instructions (0) or Thumb instruction (1). M mode control processor.
ARM abort system
Execution flow control:
Order execution
Jump instructions
Interruption
ARM kind of abort
| Abort name | meaning |
|---|---|
| Reset (Reset) | When processor reset pin is asserted, generates a reset interrupt, the program jumps to the reset exception interrupt handler executed. The system is powered, the system is reset, the reset jumps to the interrupt vector (soft reset) |
| Undefined instruction (undefine instruction) | Processor or coprocessor instruction that is currently undefined |
| Software interrupt (SWI) | Program in user mode invoked privileged operations command |
| Instruction prefetch abort (prefech abort) | Pre-fetched instruction address does not exist |
| Data Access abort (Data Abort) | Data access instruction destination address does not exist |
| External interrupt request (IRQ) | External processor interrupt request pin is active |
| Fast interrupt request (FIQ) | External processor fast interrupt request pin is asserted |
ARM processor responds to abort the process
Save the current state of the processor, the interrupt mask flag and conditions
Setting the corresponding bit in the current program status register CPSR
The return address register provided lr_mode
The Program Counter (PC), set to the address of the interrupt vector aborted, so jump to the corresponding exception interrupt handler executed at execution.
R14_ = return link ;设置返回地址
SPSR_ = CPSR ;保存状态寄存器
CPSR[4:0] = exception mode number ;设置执行模式
CPSR[5] = 0 ;运行于ARM模式
if == Reset or FIQ then
CPSR[6] = 1 ;禁止新的FIQ中断
CPSR[7] = 1 ;禁止IRQ中断
PC = exception vector addressReturn from the interrupt handler for an exception
Resume the interrupted program processor state, is about to SPSR_mode copy the contents of the register into the CPSR
Return to the command generation aborted the next instruction execution, copy the contents of the upcoming lr_mode register to the program counter PC.
Reset exception interrupt handler does not return, abort the reset handler begins execution of the user program, and thus it does not need to return
ARM System Storage System
ARM system storage space
ARM format memory
big-endian
little-endian
Non-aligned memory access operation
Unaligned instruction prefetch
Result of the instruction is unpredictable, or the value of the lowest address bit is ignored
Unaligned data access operations
For the Load / Store operations:
The results unpredictable
The lower two bits of the location address of the value is ignored; the lowest value bit of the address ignored half word units
Two low value of the location address of negligible values; least significant bit value of the address is ignored half word units