ARM architecture (two)

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The second part of the ARM architecture, mainly understands the memory interface of the CPU and the ARM startup process.

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Memory map

S5PV210 belongs to the Cortex-A8 architecture, with 32-bit address lines and 32-bit data lines, so the address space of the CPU is 4G, but due to the use of unified addressing, peripherals occupy a part of the address space, and the actual address space for memory will be Less than 4G, then the allocation of this 4G address space is memory mapping, or address mapping, the following figure is the memory mapping distribution of S5PV210, from the user manual:
description of memory distribution:

• iROM: internal ROM, internal read-only memory, ROM integrated into the SOC
• iRAM: internal RAM, internal random read-write memory, integrated into the RAM inside the SOC
• DRAM: Dynamic RAM
• SRAM: Static RAM
• ONENAND/NAND: ONENAND is a variant of NAND Flash invented by Samsung, which improves some access characteristics
• SFR: Special Function Register

Take a look at the memory distribution diagram of the iROM segment:

iROM is used to store code, iRAM is used to store data, so iROM and iRAM are separated by Not Available, which is also a reflection of the Harvard structure. We can also see that the distinction is Secure And Not Secure area.

External memory interface

Memory classification

Memory: Internal memory, used for program operation space, such as DRAM, SRAM, DDR
External memory: ROM used for storage, such as hard disk, Flash, NAND, iNAND, ONENAND, U disk, SD card, SSD, optical disk, etc.

Memory access method

The memory needs to be accessed directly, so it is accessed through the direct connection of the address bus and the data bus. The advantage is that the random access speed is fast, but it occupies a large number of bus bits and the access space is limited. From the user manual, it can be seen that DRAM0 and DRAM1 add up The memory address space of S5PV210 is 1.5G. The
external memory is not directly connected and accessed through the address bus, but is connected through the external memory interface, which will not occupy too much memory address space. The external memory address space segment of S5PV210 is: The ONENAND/NAND area of ​​0xB000_0000~0xBFFF_FFFF can expand the data storage capacity through the external memory interface, but the speed is not as fast as the memory. The access takes several cycles and the timing is more complicated.

Commonly used external storage

• NorFlash: It can be accessed by bus, it can be connected to the address space of the CPU, and accessed by memory. S5PV210 can connect a piece of NorFlash to the SROMC_BANK area to achieve memory bus access (the network card can also be connected to this SROMC_BANK area) To access), the BIOS on the desktop is actually a piece of NorFlash. If the CPU wants to access from NorFlash, it needs to access the SROMC_BANK area like this.
• NandFlash: It cannot be accessed through the bus. It needs to use the command interface to access through the timing sequence. The iROM area is used for NAND Flash to start. It is divided into SLC and MLC processes.
  
  • SLC: The capacity is small, the price is high, the timing is simple, the access is simple, and the stability is high
  • MLC: The capacity can be large, the price is low, bad blocks and bit flips are prone to occur, ECC verification is required, and access is more complicated
    
    • eMMC/iNand/moviNand: both belong to eMMC, iNAND is eMMC produced by SanDisk, and moviNand is eMMC produced by Samsung
    • oneNand: Samsung's Nand standard
    • SD/TF/MMC card: both belong to the SD card series
    • eSSD: NandFlash which belongs to the embedded MLC of SSD solid state drive
  • SATA/IDE/SCSI hard disk: mechanical access, slow speed

S5PV210 start

RAM

• SRAM: Static memory, small capacity, high price, no software initialization is required, it can be used directly after power-on
• DRAM: large capacity and low price, it is our common DDR, it cannot be used directly after power-on, and software initialization is required

External storage

NorFlash: small capacity, high price, can be directly accessed through the bus, can be read directly after power-on, generally used as a startup medium
NandFlash: large capacity, low price, can not be accessed by bus, it needs to be initialized by software after power-on, Then you can use the timing interface to access

Embedded system startup

Embedded boot medium: external NandFlash + external DRAM + built-in SRAM (iRAM)

S5PV210: 210 built-in 96KB iRAM (SRAM), and a 64K iROM (NorFlash), the startup process is as follows

• After the CPU is powered on, read the preset code (BL0) from the iROM, the address is: 0xD000_0000~0xD000_FFFF, this code performs
  
  • Initialize instruction Cache, heap, stack, block device copy function (read external startup mode), PLL and system internal clock, turn off watchdog, copy BL1 (16K) to iRAM and check BL1 checksum, safety startup related Set, and jump to BL1 to execute
  • This code is set before leaving the factory, so NandFlash and DRAM cannot be initialized for the time being, and then judge the boot mode we set through the hardware jumper, and read the bootloader from the corresponding external memory to iRAM, but the general boot code Both exceed the 96K capacity of iRAM. Samsung’s solution is to divide the startup code into 2 parts and read them sequentially:
• BL1 (configurable, maximum 16K): iRAM runs this code to initialize Flash, and then reads BL2 into iRAM
• BL2 (occupies the remaining 80K space): initialize DRAM, read OS into DRAM, and start OS
• The startup method can be seen according to this picture:
• 
• The startup flowchart is like this:
• 
  
  • WakeUp status: reset status, deep sleep or deep stop
  • OM pin: DIP switch
• If the first boot fails, the second boot will be performed, and the second boot will go through channel 2 of the SD card, as shown in the following figure:
• 
• If the SD card channel 2 fails to start, it will execute UART start,
• If the UART fails to boot, it will perform USB boot,
• If they all fail, the complete startup fails

Development board startup mode selection

The startup mode can be set through the OM pin, and set through the configuration pin. The specific settings are shown in the figure:

set according to the picture.

ARM architecture and working mode

• ARM uses a 32-bit architecture
  
  • Byte：8bit
  • Halfword：16bit（2Byte）
  • Word：32bit（4Byte）
• Most ARMs provide three instruction sets
  
  • ARM instruction set (32bit)
  • Thumb instruction set (16bit)
  • Thumb2 instruction set (16&32bit)
  • Jazelle Core also provides support for Java ByteCode
• 7 working modes
  
  • USER: non-privileged mode, most tasks are executed in this mode
  • FIQ: Fast interrupt mode, it will enter this mode when a high priority interrupt is generated
  • IRQ: Interrupt mode, enter this mode when ordinary interrupt is generated
  • SUPERVISOR: Enter this mode when reset or soft interrupt instruction is executed
  • ABORT: Enter this mode when access is abnormal
  • UNDEF: enter this mode when an undefined instruction is executed
  • SYSTEM: system mode, the kernel runs in this mode, using the same registers as USER mode
  • Except USER is in Normal mode, all others are in Privilege mode
  • All privileged modes except SYSTEM are abnormal modes
  • The mode can be switched actively by writing the CPSR register, or it can be switched automatically by the CPU
  • The permissions and accessible registers in various modes are different

ARM internal general registers

There are 17 basic general-purpose registers inside the ARM CPU, which can be defined as 37 registers according to different working modes. Each register is 32-bit. Compared with the SFR of other devices, it is more complicated. General-purpose registers pass through registers. Access by name: You

can see up to 18 registers in each mode. Although the other registers have the same name, they are all special registers for this mode and cannot be seen in the current mode.
For example, r13 (sp) and r14 (lr) in USER mode are not repeated, they are dedicated registers for user mode. These two registers do not need to consider the problem of duplication when switching modes. For the registers in all modes, see The following figure:

CPSR program status register

This register has a total of 32 bits
-0~4 are the mode bits, indicating one of the 7 modes of the processor
-5 is the T bit, which switches the processor state, 0 is the ARM state, 1 is the Thumb state
-6~7 respectively represent I, F Interrupt disable bit, I=1, IRQ is forbidden, F=1, FIQ is forbidden
-8~23 Undefined
-24 is the J bit, handles Jazelle status, J = 1, supports Jazelle, only supports ARM 5TE/J architecture
-25~ 26 undefined
-27 is the Q bit, indicating the saturation state, Q = 1, saturation, only supports ARM 5TE/J architecture
-28~31 are the V, C, Z, N condition bits:
-V = 1: indicates the ALV operation overflow
-C = 1: indicates that the carry flag of the ALV operation has overflowed
-Z = 1: indicates that the ALV operation has got a 0
-N = 1: indicates that the ALV operation has got a negative result

PC program status register

• Called the program pointer, where the PC points, which instruction the CPU will execute,
• For example, when the program jumps, the target address is placed in the PC,
• There is only one PC for the entire CPU

ARM exception handling method

abnormal

An exception refers to a process other than normal work that occurs during the running of the program. The exception will interrupt the work being performed, and it is hoped that after the exception handling is completed, return to continue the original work. Interruption is also a type of abnormality. Work in 7 The working modes except USER and SYSTEM in the mode are used to handle exceptions.

Exception vector table

• The exception vector table is a means for the CPU to handle exceptions. All CPUs have an exception vector table, which belongs to the scope of hardware design.
• When an exception occurs, the CPU will automatically act, and the PC jumps to the exception vector (exception handling address) to handle the exception, sometimes accompanied by a series of auxiliary actions.
• The exception vector table is the support provided by hardware and software to handle exceptions

ARM exception handling mechanism

• When an exception occurs, ARM Core needs:
  
  • Copy CPSR to SPSR_<corresponding mode>
  • Set the appropriate CPSR
    
    • Change the processor state to enter the ARM state
    • Change the processor mode to enter the corresponding exception mode
    • Set the interrupt prohibition bit to prohibit responding to interrupts to prevent exception handling from being interrupted
  • Save the return address to LR_<corresponding mode>
  • Set PC to the corresponding abnormal vector
• When the exception returns, ARM Core needs
  
  • Restore CPSR from SPSR_<corresponding mode>
  • Recover PC from LR_<corresponding mode>
  • The above operations are carried out in the ARM state
• Some exceptions are handled automatically by the CPU, and some require manual operation by the programmer. The exception vector table provided by the CPU is generally a first-level vector table. In order to support multiple interrupts, some CPUs also provide a second-level vector. Table, the processing method is similar to the first-level vector table.