Overview of ARM (based on Chapter 1 of ARM Architecture and Programming)

AMR overview

The ARM processor is a 16 / 32-bit embedded ¹ RISC microprocessor with high performance, low cost and low power consumption . Because of these characteristics, it has become the most widely used embedded processor. Engaged in the embedded industry, it is necessary to study it systematically, in-depth understanding of the chip architecture and mastering its working principle, which is very helpful for the subsequent low-level learning (boot, kernel, file system), and also for strange-shaped bug Have more accurate positioning. If you want to design a system with good performance, you should not be unfamiliar with the ARM architecture.

Operating mode of the ARM processor

There are 7 operating modes for the ARM processor, as shown in the figure:

the other 6 processor modes besides the user mode are called the privileged mode . The privileged mode here means that programs in this mode can access all systems Resources, and arbitrarily switch the processor mode. In addition to the system mode, the other five privilege modes are also called abnormal modes .

The switch between the different processor modes mentioned above can be switched by software by modifying the corresponding flag bit (CPSR) ² . It can also be switched by external interrupt or exception handling. When an abnormal interruption occurs in the system, the processor enters the corresponding abnormal mode, and each type of abnormal mode has a set of registers for the corresponding exception handling program, so as to ensure that the registers in the user mode are not destroyed ³ .

Programs that normally run in user mode want to access system resources only through soft interrupt (SWI). Common system calls (read write) access system resources through SWI.

ARM register

There are 37 registers in the ARM processor. Including:

=> 31 general registers. There are R0-R14, PC.
1. No backup registers (R0-R7), all modes are common, and there is a competition relationship. When the mode is switched, the data in it will be changed.
2. Backup register (R8-R14): Among them, there will be an independent R8-R12 ⁴ only in the fast interrupt mode , shared by other modes. Because R13 is commonly used as a stack pointer, R14 is used as a connection register, R14 can be used to save the abnormal return address and the return address of the current subroutine . So these two registers have corresponding physical registers in each mode.
3. There is only one program counter R15, no matter what mode it is in, because this is the register that the program needs to run instructions. ARM processor has taken the pipeline mechanism ⁵ , so there is a deviation PC register address and the current instruction execution, how many need to refer to the specific architecture of ARM processors.

• note: Special attention is required when copying to PC, when running ARM finger set. ARMV4 and higher instruction set versions can only copy data that is word-aligned (that is, the lower two bits are 00), otherwise an error will occur . The version with a low instruction set can be copied at will (it is best not to be too random, to form a good habit), ARM will automatically ignore the lower two. The system will ignore bit0 data when running the thumb instruction set. The BX instruction will also use bit0 of the PC to distinguish between the thumb instruction set and the arm instruction set.

=> 6 status registers, including CPSR and SPSR in abnormal mode (since the program runs in normal mode, there is no SPSR in normal mode). The format and introduction are as follows:

Abnormal interruption of ARM system.

Types of ARM interrupt

Each type of abnormal interrupt in ARM has its own backup register set. See the previous section for details. When multiple exception interrupts occur in ARM at the same time, you can choose to respond to the exception interrupt with the highest priority according to the priority of each exception interrupt.

ARM processor response flow to interrupt

The response process of the ARM processor to abnormal interrupts is as follows:

• Save the contents of the processor's current program status register (CPSR) to the stored program status register (SPSR) corresponding to the abnormal interrupt to be executed.
• Set the corresponding bit in the current program status register CPSR, disable IRQ, disable FIQ ⁶ and set to the mode to be entered.
• Set register Lr_mode to return address ⁷ .
• Set the program counter (PC) to the interrupt vector address of the abnormal interrupt, so as to jump to the corresponding abnormal interrupt handler.

Start interrupt processing ...

• Restore the contents of the interrupted program status register.
• Return to the next instruction of the instruction where the abnormal interrupt occurred, and copy the value of R14 to the program counter (PC).

Storage system in ARM system

Here only briefly explain the storage format of ARM, there are words, half words, bytes in the ARM system. In storage, it is better to observe word alignment for word units and half word alignment for half words. For non-aligned storage, the result of the execution may be unpredictable during the access or the low-order bits in the access address are ignored (half-word low 1bit, word low 2bit)
Here by the way, the big and small end of the storage, the big end storage: low Address stores high byte data; little endian: low address stores low byte data, as shown below.

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1. Embedded system refers to the application-centric, computer technology, hardware and software can be tailored to meet specialized computer application system functionality, reliability, cost, size and power requirements of strict ↩︎

2. The prerequisite for software switching is that the current processor is already in privileged mode. ↩︎

3. The system mode is not entered through an abnormal process. The system enters the system mode when power is turned on. It has exactly the same register set as user mode. ↩︎

4. Because the fast interrupt mode requires the processor to quickly handle exceptions, it is equipped with independent R8-R12 registers to reduce the saving and recovery operations of the registers, thereby reducing the switching time. ↩︎

5. When the instruction is executed, the processor will obtain the instruction to be executed later. ↩︎

6. In the process of exception handling, FIQ and IRQ need to be forbidden, or else they will respond to other exceptions before the exception has been handled. ↩︎

7. There is a conversion when saving the return address, which needs to be calculated according to the specific chip. ↩︎