From the history of the development of ARM begin to S3C2440 for example were compared with 51 single, detailed analysis of the ARM architecture.
First talk about the history of the development of ARM: December 5, 1978, physicist Hermann Hauser and engineer Chris Curry, in Cambridge, UK company founded CPU (Cambridge Processing Unit), the main business is the supply of electronic equipment for the local market. In 1979, CPU company changed its name to Acorn Computers.
The mid-1980s, Acorn, a small team to pick for their next generation of computer suitable processor, according to the technical requirements they provide, can not find a suitable processor in the current market, so a Acorn decided to design their own processors. A small team in just 18 months to complete the whole process from design to implementation, which is a RISC instruction set computer, called the Acorn RISC Machine (referred to as ARM). Later Acorn's decline, while the processor design department is divided out to form a new company.
The company ARM ARM designs AISC series processor cores, it does not produce chips only provide IP core. An example of the first to explain architecture, core, processor and chip: S3C2440, which is a SoC chip, note that it is not the cpu, 2440 and 51 single-chip we know a little bit similar, are all embedded, embedded development to currently we are gone through three stages, namely, SCM, MCU, SoC. 51 belongs to the SCM or MCU, and 2440 belong to the SoC, first look at the internal structure of the microcontroller 51
Its internal structure can be simply divided into two parts: cpu and peripherals. Look at 2440:
The middle of the arm920t is its processor, processor core, and in my opinion is a concept here, only one is a hard concept, a soft concept. 920t here on both a processor and a core. Samsung to do is cpu addition to this other stuff.
That structure? Look at a map.
Which is to the left of the structure, on the right side of the processor, it can also be called core. The first arm is the most successful cpu ARM7TDMI, is based on the ARMv4. ARM RISC architecture includes the following features:
Load / store architecture
Does not support unaligned memory access address (kernel now supports the ARMv6)
Orthogonal instruction set (arbitrarily access any addressing mode instructions may access data Orthogonal instruction set)
The large 16 × 32-bit register array (register file)
32 bits fixed operation code (opcode) length, the amount of code generated by reducing cost, reducing the burden of decoding and pipelining.
Most are a CPU cycle execution.
Different versions of the framework will be adjusted.
Major manufacturers Samsung and the same arm and other cooperation will usually its CPU and various peripheral IP are put together, then took his drawings to the flow sheet, is produced by a square, following a lot of pins, this thing not only includes the CPU, also includes other controllers, this thing called SOC (system on chip). From the English point of view, the so-called quad-core SOC something, it is not intended to refer to a single CPU, but quad-core systems.
So now the major manufacturers doing things, is authorized to buy ARM, the ARM processor to get the source code, then their practice some peripheral IP (or buy or own design), composed after a SOC, go taped. SOC different, different architecture (CPU that is IP and how to contact them, some with bus as the core, some with DDR core), so that the Hass has a SOC architecture is proprietary. However, regardless of any vendor, no matter how frustrating, not how moving through CPU, ARM core on good stay there, and that is the central processor.
Currently ARM products Ladder:
ARM naming rules:
The first number: Series name: eg.ARM7, ARM9
Second number: Memory system
2: with MMU
4: with MPU
6: No MMU and MPU
The third number: Memory size
0: Standard Cache (4-128k)
2: the reduced Cache
6: Variable Cache
The fourth character: T: Thumb instruction set support
D: that debugging (Debug) on-chip support
M: represents embedded hardware multiplier (Multiplier)
I: supports on-chip breakpoints and debug point
E: support for enhanced DSP functions
J: support for Jazelle technology, the Java accelerator
S: represents the total synthesis of formula