Basic theory of ARM architecture
1. Introduction to ARM
ARM (Advanced RISC Machine) is a computer processor architecture based on RISC (Reduced Instruction Set Computing) architecture, developed by ARM Holdings (ARM company) and licensed to other companies for production and sales.
The ARM architecture was originally designed for low-power, high-performance embedded systems, such as smartphones, tablets, digital TVs, routers, audio equipment, controllers, and more. With the development of technology, ARM processors are gradually applied to more fields, such as servers, supercomputers, etc.
ARM processor has the advantages of low power consumption, high efficiency, scalability, reliability, etc., so it has been widely used. At present, the ARM processor has become one of the most commonly used processor architectures in mobile devices and embedded systems, and is also one of the most popular processor architectures in the world.
The instruction architecture of the processor is divided into:
- CISC (Complex Instruction Set Computer): complex instruction set, CISC CPU contains a wealth of unit circuits, so it has strong functions, large area, and high power consumption. There are a large number of instructions and addressing modes, and the frequency of use of various instructions varies greatly. Among them, 80% of the programs only use 20% of the instructions , and most programs can run with only a small number of instructions. Therefore, people have simplified the instruction system, and combined complex instructions with simple instructions, thus forming a RISC instruction set.
- RISC (Reduced Instruction Set Computer): Simplify the instruction set, select some simple instructions with the highest frequency of use, the functions of complex instructions are realized by the combination of simple instructions, only the Load/Store (fetch/store) instructions are accessed, and the rest instructions are All operations are performed between registers. Special emphasis is placed on compilation optimization to reduce program execution time. From the perspective of command system compatibility, most CISCs can achieve software compatibility, that is, high-end machines contain all the instructions of low-end machines and can be expanded. However, RISC simplifies the instruction system, the number of instructions is small, and the format is different from that of old machines, so most RISC machines are not compatible with old machines.
For example: there are N instructions, and the running time of each instruction is T, while the running time of CISC instructions is T1=N*T, and RISC instructions can decompose one instruction into 3 instructions (fetch instruction, decode, execute) . , the time of each instruction is T/3, then T2=(N+2)/3*T
2. ARM technology
1. The basic data types of ARM
ARM adopts a 32-bit architecture, and the basic data types of ARM are as follows.
Byte: byte , 8bit.
Halfword: Halfword , 16bit (halfword must be aligned to a 2-byte boundary).
Word: word , 32bit (words must be aligned to 4-byte boundaries).
Word boundary alignment is based on 0, 4, 8... as the first address, that is, the lower 2 bits of the first address must be 0 (0000, 0100, 1000, 1100).
Halfword boundary alignment is based on 0, 2, 4... as the first address, that is, the lower 1 bit of the first address must be 0 (0000, 0010, 0100, 0110).
2. Two working states of the processor
ARM state: 32-bit, ARM state executes word-aligned 32-bit ARM instructions.
Thumb state, 16 bits, executes halfword-aligned 16-bit instructions.
Use the Bx Rm instruction to switch between the two states:
Bx is a jump instruction, and Rm is a register (1 word, 32 bits). If the bit of Rn is 1, enter the Thumb state; if the bit of Rn is 0 , which enters the ARM state. (Reason: The last two bits of the ARM instruction are always 0, which is useless, while the last bit of the Thumb instruction is always 0, which is useless, so bit 0 is used to indicate the switching flag between the ARM instruction and the Thumb instruction.) ARM instruction
set Relationship with the THUMB instruction set:
The THUMB instruction set is a subset of the ARM instruction set, and all Thumb instructions have corresponding ARM instructions. Thumb's architecture is not very complete, so it cannot require a processor, only supports Thumb code, but does not support ARM instruction set. The Thumb code supports general functions well, and for some non-general functions, the ARM instruction set can be borrowed. So applications can mix ARM instructions and Thumb programs to improve performance and code density. At the same time, power consumption can be reduced and costs can be saved.
3. Two storage formats for ARM processors
The ARM architecture can store data words in two ways, called Big-Endian mode (Big-Endian) and Little-Endian mode (Little-Endian).
(1) Big-endian mode : In this mode, the high byte of the 32-bit data word is stored in the low address, and the low byte of the data word is stored in the high address.
(2) Little-endian mode : It is completely different from storing data in big-endian mode. In little-endian mode, the high byte of the 32-bit data word is stored in the high address, while the low byte is stored in the low address.
It is generally customary to use little-endian mode.
4. Working mode of ARM processor
5. 31 general-purpose registers
R13(SP): point to the stack, protect the interrupt program.
R14 (LR): link register, return address.
R15 (PC): Program counter, pointing to the address of the next instruction to be executed.
CPSR: Status Register.
Program jump where an interrupt occurs:
6. Status register
(1) Condition code flags
N, Z, C, V, the highest 4 bits are called condition code flags. Most of ARM's instructions can be executed conditionally, that is, by detecting these condition code flags to determine how the program instructions are executed.
N: In the case of signed two's complement, N=1 if the result is negative; N=0 if the result is non-negative.
Z: If the result is 0 , then Z=1; if the result is non-zero, then Z=0.
C: For the addition instruction (including the comparison instruction CMN), if a carry is generated, then C=1 ; otherwise C=0. For subtraction instructions (including the comparison instruction CMP), if a borrow is generated, then C=0 ; otherwise C=1. For an illegal instruction with a shift operation, C is the value of the last bit shifted out in the shift operation. For other instructions, C is generally unchanged.
V: For addition and subtraction instructions, when the operand and the result are signed integers, if overflow occurs, then V=1; if no overflow occurs, then V=0 ; for other instructions, V usually does not change.
(2) Control bit
I: When it is 1, the IRQ interrupt is disabled, and when it is cleared, the interrupt is enabled.
F: When it is 1, the FIQ interrupt is disabled, and when it is cleared to 0, the interrupt is enabled.