Computer System Structure and Composition - Chapter computer logic components

Computer logic components:

• A combinational logic circuit:
  • Definition: If the output state of the logic circuit and only then enter the relevant state, regardless of the input state in the past, saying that logic is a combinational logic circuit
  • Commonly used devices:
    • Tristate circuit:
      • Uses: an important bus interface circuit
      • Tri-state:
        • Normal 0 state: the output impedance is very low, also known as the low-resistance state 0
        • Normal state 1: output impedance is very low, also known as a low resistance state
        • High impedance Z: output a high-impedance, it can be considered "off"
      • Menu and logic diagram:
        • 
      • Applications:
        • 
        • Number of tri-state gate drive common bus is the most common application. And the bus can not "on", otherwise disrupt the normal operation of the bus
        • For reliable operation, the tri-state circuit from normal state to a high resistance state is always faster than the process of transition to a high impedance normal state of
    • XOR gate:
      • Menu and logic diagram:
        • 
      • application:
        • Original code / anti-code output circuit:
          • One input terminal of exclusive OR gate as the control terminal, the other input terminal for a digital input terminal
          • Obtained by the function table: When the control terminal is 1, the output is inverted input; is 0 when the control terminal, the output of the input original code
          • Example:
        • Half adder:
          • Irrespective adder carry input
          • When the two digital A _I , B _I , do arithmetic addition (called semi-additive); as long as the A _I , B _I applied to the input of the XOR gate, the XOR gate function is clear from the table, the output of the Y _I is the semi-additive and
          • Example:
        • Digital comparator:
          • Digital A _I , B _I ; applied to an input terminal of the XOR gate, the menu can be seen therefrom: When A _{I =} B _I, then the Y _I = 0; when A _I ! B = _I,  then the Y _I =. 1
            
          • Example:
        • Parity detection circuit:
          • FIG. 2.8 is eight parity detecting circuit, when A _0-7 contains an odd number 1, F = 1; when A _0-7 when an even number of 1, F = 0
          • 
    • Adder:
      • Half-adder
      • Full adder:
        • Consider adder carry input
        • X- _n- , the Y _n- and carry input C _{n-. 1-}  sum called full addition, the operation result F. _N-  called full additive
        • Menu:
        • And FIG logical expressions:
        •  
        • 
      • n-bit adder:
        • Principle: The n full adders can be connected to an n-bit adder to give
        • Disadvantages:
          • Addition long time
            • Because the inter-bit carry which is serial transmission, and a standard full-adder F. _I must wait for the carry low C _{I-. 1} came to be in order, and the number of digits for adding time
            • Only by changing the bit-by-bit transfer path forward in order to improve the operating speed adder
        • solution:
          • A " look-ahead generator circuit " formed simultaneously carry you, enabling rapid addition, which is called an adder -lookahead adder
            • Lookahead generation circuit:
              • Generating lookahead circuit is formed according to the conditions you carry achieved, the introduction of the carry transfer function P _I and the carry generation function G _I to simplify the expression
    • An arithmetic logic unit (ALU):
      • Various arithmetic and logic operations of the combinational logic circuit
        
      • Basic logical configuration is lookahead adder
      • By changing adder G _I and P _I to obtain more computing power
      • Example:
        • 4 with "four adder" circuit can be composed of 16-bit ALU
          
        • 
        • (The group) chip is a fast carry between sheets (groups) is piecewise carry transfer
        • Forming F. ₀ ~ F. ₁₅ time is relatively long
        • Improve:
          • If the above 16-bit ALU is used as each set of four bits forming method similar four lookahead adder "meta fast carry" to achieve 16-bit ALU in " groups fast carry ", introducing 4 carry generating a set of function G _N, then you can obtain a fast 16-bit ALU
          • 
    • decoder:
      • O:  n-input variables, 2 ^n- th (or less than 2 ^n- th) output .. When the input is some combination, only one output corresponding to 0 (or 1), and the remaining outputs are 1 (or 0), E = 0 is often set to "Enable", "control terminal E, when, decoding function is disabled, all outputs are 1 (or 0)
      • Uses: is the input code is translated into a corresponding control voltage to achieve the required operation code
        
      • Extended:
        • Example:
          • 2 inputs and 4 outputs logic diagram of the menu:
          • 3 2 8 outputs of the decoder input into a spreading output of the decoder 16 input 4
          • 
    • Data selector (multiplexer selector switch or multiplexer):
      • O: select a data channel from a plurality of input channels as an output
      • Extension: enable terminal may be used to expand the number of channel selector
      • Example:
        • 
        • S ₀ , S _{. 1} is a channel selection signal
        • G is a tri-state control terminal, the selector can be used to expand the number of channels
        • D ₀ ~ D _{. 3} the input data

 

• Sequential logic circuit:
  • Definition: output state of the logic circuit only when the input and about the status, but also with the input state of the logic circuit heretofore associated circuitry
  • Common devices:
    • trigger:
      • Status: the memory element storing information, that form the basis of a timing circuit
      • kind:
        • Potential trigger trigger:
          • Features: simple structure, used to make up the register
          • Example:
            • Locking flip-flop (latch):
        • Edge-triggered flip-flop mode:
          • Input : receiving a clock pulse CP is a convention transition (positive or negative-going transitions) to the input data, and the CP = 1 and CP = 0 during the transition when the arrival of non-conventional CP, the flip-flop is not Receive data 
          • Positive edge-triggered: only receive data on the rising edge
          • Negative edge-triggered: only receive data until the next rising edge
          • Example:
            • D flip-flop:
              • Menu and logic diagram:
              • : Features capacity data terminal having a strong anti-interference
                
              • Uses: it can also be used to compose registers, counters and shift registers
        • Master - slave trigger trigger:
          • Composition: basically triggers a cascade of two potentials obtained by receiving an input data is a master flip-flop, the flip-flop receives the output from the master flip-flop, the main synchronization control signal from the flip-flop is complementary to
          • Example:
            • JK flip-flop:
              • Menu and logic diagram:
              • Uses: Due to master flip-flop with a counter, the counter used in the composition
    • Register and shift register:
      • Uses: it is an important part of a computer, for temporarily storing data and instructions, etc.
      • Composition: flip-flops, some of the control gate
      • The shift register: a shift register function, the control logic circuit to increase the input data flip-flop
      • Example:
        • 4-bit register
        • D flip-flops triggered by a positive edge of the 4-bit register composed of
        • CP positive effect in the edge, to the external data into the register
    • counter:
      • Uses: The computer of one meter and a digital circuit common
      • Synchronization: Each trigger pulse from the same clock signal, the flip-flops are inverted simultaneously
      • Example:
        • A decimal synchronous counter:
          
        • Flip-flops in each counter clock pulse signal is provided by the same, at the same time each flip flop
        • Using fast way to count the carry, and the core together with the trigger counter
        • Preset count: an important function

 

• Array logic circuit:
  • Array: refers to the logical elements are arranged in an array on a silicon chip
  • Features: There are user-programmed to reduce the size of the system's hardware
  • kind:
    • ROM (Read Only Memory):
      • Word: number of binary information consisting of
      • Bit: Each binary information
      • The storage unit: means for storing information, a word composed of
      • Address (address): for each word in the memory number stored in the word for finding
      • Composition: address decoder, a storage unit
      • Capacity: generally indicated by the "wordline, bitline ×"
      • Storing information indicates: to represent binary information stored by setting or settings, such as transistors, diodes, or the fuse element 
      • Working principle: an address decoder to select one of output (called a word line) in accordance with the input address, which go by the driving of the word line bit line, word line to read out the code stored in each memory unit,
      • Disadvantages:
        • When the user to be stored in ROM ROM of words than words can provide, there are many ROM storage unit will be idle, resulting in waste of die area
        • In the ROM, there is one to one relationship between the address and the words, for any given address, only one word read, and therefore, even if the content of the same number of words, can not save unit
      • structure:
        • 
          
    • PLA (programmable logic array):
      • Composition: array, or an array
      • Use: There are widely used in the composition of the controller, and storing a fixed function implemented in random logic
      • Features: with less storage unit can store a large amount of information
    • PAL (programmable array logic):
      • Features:
        • And the array is programmable, or programmable arrays are not
        • Programming is disposable, i.e. can not be programmed rewritable
        • In certain PAL device is further provided memory element, may also have a feedback function, i.e., the output may be fed to an output terminal, an input signal is used as
    • GAL (Generic Array Logic):
      • Features:
        • Available electrical erasable, reprogrammable high speed PLD (Programmable Logic Device)
        • Erasable and rewritable more than 100 times, data can be stored for more than 20 years, in a few seconds to complete erasing and programming process
        • A logical output macrocell, by its programming, a variety of output forms can be obtained, thereby greatly enhanced
    • GA (gate array):
      • Usage: used to achieve production of large quantities of specific integrated circuit (ASIC)
      • User device half (semi-custom devices): the master process completed most of the entire integrated circuit manufacturing process, when the user submits a logic diagram, as long as the interconnection between the base unit and the base unit internal wiring it
      • Features:
        • Using pre-fabricated "master" is usually performed at a constant pitch arranged in rows and columns on the basic unit circuit layout designs, the master
        • A semi-user device
        • Design Automation higher
        • Shorter design cycles
        • Low cost design
    • The MCA (macro cell array):
      • Composition: door improved array, generate a macro cell array, a macro cell is constituted by several elementary cells
      • Features:
        • Logic function relatively strong, and therefore a higher density than the layout gate array
        • The user device is a semi-
        • Short manufacturing cycle
    • The SCA (normal cell arrays):
      • Standard cell (cell polyols): pre-designed functional unit may be a door, a certain function or trigger function blocks (such as adders)
      • Composition: standard bit base unit
      • Features:
        
        • All units are needed in the user logic on the chip arrangement of FIG.
        • Layout and easy to implement
        • A user device can not be produced in large quantities in advance semifinished chip good
    • FPGA (field programmable gate array):
      • composition:
        • Programmable logic macrocell (the CLB)
        • Programmable Input Output Macrocell (lOBs)
        • Interconnect resources
        • Reconfigurable logic rewritable memory
      • Features:
        • LSI constituted by the door Circuits reach tens of thousands to millions
        • It allows the user to edit multiple logical

 

Reference - "Computer Organization in structure" - Tsinghua University, Wang Aiying