Memory Controller
A memory chip, if you want to access it, you need to address lines, data lines, chip select lines, write enable, read enable and other control lines, of course, can themselves be controlled by IO timing simulation, but too much trouble, there is a memory now S3C2440 the controller may help us to get the logic control, we only need to use the memory performance, compared to a timing chart relevant register is provided to memory controller good.
View S3C2440 manual, you can see the relevant characteristics are shown, including, but not limited to:
1. The size of the end of the software may be provided
2.8 Each bank a total of 128MB 1GB of memory which can control the maximum you can to 1GB (if all were using words)
3. In addition to bank0, programmable access to bits 8/16 / 32bit, bank0 may be provided 16/32
Bank at 4.8, 6 may be used ROM, SRAM and the like, can be used in two ROM, SRAM, the SDRAM, etc.
5.8 bank seven fixed location, can be accessed as an offset
6. A flexible adjustment start address and size of the bank, means bank7
7. Support and self-refresh mode for low-power SDRAM.
It can be seen from the block diagram of the memory map, the presence of the two methods NandFlash and NorFlash S3C2440. When started NorFlash manner, the initial value of the register 2440 can be sufficiently slow so norflash driven directly mapped to BANK0 norflash this case, the embedded SRAM are mapped to the bank7. SUMMARY front 4KB of memory when starting to NandFlash manner, NandFlash 2440 will be copied to the built-in SRAM, and the SRAM is mapped to the start address at this time, this time nGCS0 invisible, i.e. NorFlash unavailable. Specific started by which way, OM1 is determined by the pin OM0, and should be determined well before the first access memory.
JZ2440 binding principle chart, OM1 has been connected to the ground level GND 0, the other end of a grounding switch control 3.3v power alive, and determines to start NandFlash or 16bit NorFlash start mode.
Norflash way can also be seen on the diagram, the used model MX29LV160DBTI norflash, as can be seen in FIG pins used comprising: a power pin, address lines, data lines, read enable, write enable, chip is selected from (Nxxx indicates low active), it can be seen from the data lines of the chip 16 chip, provides a 16-bit wide data, using the data line 20, compared with 2 ^ 20 = 1M * 16bit = 16Mbits size. But it is strange that the address lines A1 received A0, rather than A0 A0 corresponding to the connection. There are examples in this regard S3C2440 chip manual:
Here is my understanding, S3C2440 address lines designed to access address addressing data width of the chip 8, when a flash 8-bit wide, docking A0 A0, the address of each address are aligned. When using the flash 16 bit wide, A1 and A0 docking, i.e. the address / 2, can also be understood as a binary one, for example, when addressing the need to address 0, A0 is 0, A1 is 0, this when accessing the address data is 0, the read 16-bit data, when the address is 1, A0 is 1, A1 is 0, this case still read address data 0, and when the address reaches an integral multiple of 2, A0 is 0 , A1 is 1, then reads out the second 16-bit data. Of course, not useless A0, A0 can be used to distinguish the required 16-bit data upper 8 bits or lower 8 bits. 32-bit Flash so, A2 then A0, A1, and A0 with 8 to determine which data need to use the read 32-bit data, of course, this value depends on the orientation of our instruction bit width used instruction width, if LDR, direct access to the 32-bit, if LDRB, 8-bit data is taken therein.
Read the manual of the chip will know that we have set in the register set is the number of bits used in the chip, I think this is how many bits are used to set the receive buffer used, and can also be used in accordance with the above-mentioned A0 or A1 to remove the desired data bits wide.
In addition to the memory controller data sorting function, as well as signal processing hardware logic function, i.e., chip select, write enable and read enable control signals and the like, we need to set up only between the respective signals depending on the performance of the chip used time interval, the memory controller will send a corresponding control signal we use to an upper layer when the logic, thereby reducing the development burden, particularly with reference to a timing chart of the time required and the chip manual contrast to when speaking NorFlash and SDRAM. In addition, the memory controller 8 Bank-mapped address and the address register of unified addressing specific chip can view the manual, set up after the relevant registers, mapped directly to the memory controller can read and write address.
NorFlash
This section describes the JZ2440 use to MX29LV160DBTI NorFlash parameters and timing diagrams and control need to know those things.
The chip can see the manual page for the most critical feature of the chip has been given parameters, the size of 16Mbits, can, 3V power supply needed to eight (2M memory cells) or 16-bit (1M storage unit).
Turned down, a logic chip pin can see the symbol table, the table indicates, the NorFlash the address lines, data input and output lines, chip select, write enable, word / byte selection input, reset, read enable, busy state output, and the power supply line and the acceleration hardware write protection pin. Wherein the pin is pulled inside the acceleration exists, if not need to use floating or connected to high level to make them inactive.
Q15 / A-1 not initially appreciated that what is meant by the reference to the text can know that A is A-1 1 negative, i.e. after a combined AM-A0 address bit A-1. 16bits bit width of the chip, the storage unit 1M, address all memory cells can be accomplished by co-A0-A19 address line 20, and the bit width is 8bits, addressed memory cells require doubling requires a multi-address line, this time, the data lines can be used as the idle address lines are multiplexed, so that the table is described.
Further down is a block diagram of the chip, the control is directly related to our control input is a logic block coupled to the control pins, the address latch and buffer blocks, buffer IO data. External logic control module will control signals to other internal modules, such as the write state machine. Address input address block will be split to the output X, Y decoding, X is decoded word line address, Y address decode the bit, so the address addressed by flash array, where the array is a bit like a program array [x ] [y] two arrays, i.e. we address decode chip address is recognizable. Data, the voltage output by the amplifier to achieve the proper data to the IO buffer by Y-pass gate circuit. We know NorFlash not be the same as the conventional direct write, need special commands to write, and yet when we send out control signal WE, IO data will be latched to the data latch command (command data latch), followed by the same be decoded, converted to "internal language" chip output to the status register, and the status register driven state machine commands in the corresponding state operation, as we write the desired data, can be seen the state machine is really versatile and good use. Program / ERASE high Voltage manual see description of this module provides the control logic high I appreciated device (probably misunderstood) to a corresponding module, to meet the relevant logical device is charged and discharged to remove or set (bit 0/1 ) potential function.
The following table lists the commands and corresponding operation states of the pins and, on the block diagram corresponding to the control unit, where in fact, GPIO pin can be ordinary analog command control purposes, but now we have memory controller, which It will help us deal with these.
While concerned about the following diagram showing the need to address some instructions and data input within a fixed period of time, so that the chip's internal state machine can be operated to our desired command. This layer is a logical implementation layer, needs to be in the pre-write-enabled state is ensured by the memory controller, the rest of the program it is necessary to implement the function corresponding.
Need to focus attention on the relevant time explaining the timing diagram, will come back to see the timing diagram according to this table.
Norflash chip timing diagram on a lot of the manual, here we can use to refer to the manual S3C2440 chip schematic, extract a timing diagram corresponding NorFlash to simplify the work.
First, find the S3c2440, only two read and write timing diagrams related NorFlash, first reading :
At the same time find a timing diagram of read NorFlash in:
Controls the schedule described above can know in which time appears as meaning:
Tce: chip select signal CE sent long after the data is valid
Tsrw: state transition time interval between the read and write
Toeh: Output Enable bit to keep that needs to write enable WE invalid after time after Toeh can enable OE
Toe: OE Toe time elapsed after enable data to be effective
Taa: the address signal sent via the data valid time Taa
Trc: Read cycle time, during which time a read operation
Toh: CE and OE is inactive after the data retention time and the address
Tdf: floating output data of invalid time after OE and CE, i.e. the data over the time period is uncertain
In the S3C2440, Tacs address signals chip enable requires much time before the issue, there is no requirement NorFlash and therefore to 0; Tcos enable CE is a need to enable OE how long ago sent, there is no requirements, set to 0, i.e. simultaneously S3C2440 will send an address signal, the chip select signal CE, an output enable signal OE. Tacc is the time after which data can be efficiently S3C2440 output control signal, and the NorFlash Taa, Tce, Toe relevant, since we also issued three signals, and therefore can select the Taa longest, because it is the experiment, we choose the most after long 70ns, 70ns i.e. three control signals can be output to read data. Tacp not marked in the NorFlash therefore set to the minimum value. Tach Tcoh and three control signals is sequentially showing invalid time interval, there is no need to set to 0. Concern is NorFlash data output after some time floating, the chip manual given is 30ns, here we are a bit tricky, because the next time reading always need to read the output after 70ns three control signals, so no Watch the float time. I write to find time to read involves timing diagram is the same, so the analogy can be interpreted, not expand here.
In summary, the start register S3C2440 provided, involving the BWSCON, BANKCON0, as is used to BANK0, and is the NorFlash, so other related SDRAM can not set.
BWSCON to set the first bit width, as here bank0 boot area, has been determined by the boot and OM1 OM0 is 16bits, so here register is read only, it need not be provided.
It followed BANKCON0, which is time-related settings, here as well just set associated with NorFlash can be. Here all the time period represented by the time, and the memory controller block diagram view S3C2440 clock can be hung on the HCLK know the bus, while the previous exercises, HCLK is set to 100MHz, so here is a 10ns clock, so Tacs and Tcos set to 0, Tacs set to 8clock (very conservative option, in fact, may be lower, because the chip manuals and no minimum value, if not to zero, should be able to be tested).
Output code is as follows:
s3c2440.h
-----------------------------
#ifndef __S3C2440_H
#define __S3C2440_H
#include <stdint.h>
.....
//memory controller
#define BWSCON (*((volatile uint32_t*)0x48000000))
#define BANKCON0 (*((volatile uint32_t*)0x48000004))
....
void HardwareInitAll(void);
void Delay(uint32_t time);
void MemoryControllerInit(uint32_t val);
#endif
s3c2440.c
----------------------------
......
void MemoryControllerInit(uint32_t val)
{
BANKCON0 = (val<<8); //此处不能像之前那样清零控制位后再设置，置位0时NorFlash读取异常，将死机
}
void HardwareInitAll(void)
{
WatchDogDisable();
/*调试过程发现norFlash启动时，ClockDevideConfig必须在MPLLConfig前设置
*应该与MPLL设置时的locktime相关，在norflash启动时速度较慢，分频来不及在
*locktime结束前设置，而nandFlash则足够时间*/
ClockDevideConfig();
ChangeModeToAsynchronous();
MPLLConfig();
MemoryControllerInit(7); //8 clock
}
#include <stdint.h>
#include "s3c2440.h"
#include "led.h"
#include "uart.h"
int main()
{
HardwareInitAll();
LedInitAll();
UartInit();
uint8_t led_now=kLed1;
uint8_t i=0;
uint8_t tmp;
while(1)
{
tmp = getc();
putc(tmp);
//实验证明到3的时候已经停止运行了，推测因为30ns浮空时间的限制
if(tmp <= '7' && tmp >= '0'){ tmp -='0'; }
MemoryControllerInit(tmp);
i=6;
while(i--)
{
SingleLedOFF(led_now++);
if(led_now > kLed3) { led_now =kLed1; }
SingleLedON(led_now);
Delay(100000);
}
}
}
SDRAM
With the knowledge of the bedding front, SDRAM will be easier to understand. First, the first on-board look schematic JZ2440 SDRAM, a total of 32 data lines, two of an SDRAM memory 32, the address line A2 to a SDRAM of A0. Manual from the SDRAM chips can be seen as a capacity of SDRAM 16M * 16bits, thus addressing the need for the memory cell has a 16M, the address lines should be 24, but uses only figure A2-A14, and with A24- A25 is connected to the BA0 and BA1, which is determined by the access mode of SDRAM.
SDRAM as a block diagram, it can be seen where the SDRAM memory is divided into four Bank, each bank 4M * 16bits, col and row addresses needed to access memory cells therein. Therefore, to provide access to the SDRAM bank address needs to sequentially determine the bank, is determined to provide row line, column COL determined, a certain time is required between the row and col, which is a control parameter Trcd. The content is relatively simple block diagram will not go, NorFlash analogy can clearly understand.
Registers need to be set as follows:
Can be seen from the schematic, using bank6 S3C2440 SDRAM memory controller, it is only necessary to set Bank6 related registers, on two parallel board SDRAM is 16bits 32bits memory, so DW6 to 10. WS6 bit wait enable bit, but when reading S3C2440 SDRAM is busy can not respond to the data, the SDRAM can be set so that the bit 2440 to wait for some time, there is no use, directly disable. ST6 is the only operation of its kind byte change when setting SDRAM multi-byte read or write, is set to 0 only written this effect, set to a read and write have the effect, here we have read memory controller to help picking data, and therefore can be set to zero.
MT is set to 11 means that we are using the SDRAM, the middle section Tacs-PMC for non-SDRAM and therefore ignore them. Trcd is the time Row and Col address the above-mentioned interval, manual search SDRAM chip, you can know a minimum of 18ns, so use 00, that is 20ns. SCAN represents the column address bits SDRAM view SDRAM chip manual search column address, you can know the column address bit SDRAM used for the A0-A8, namely 9, and therefore is set to 01.
SDRAM is a dynamic memory, need to be refreshed to maintain data, or you may lose data, refresh here is actually stored in the capacitor to recharge. REFEN use the default Enable refresh. TREFMD set to automatically refresh mode. Trp after how long the chip select signal sent to the row address enable, or transferred to another access line from one row precharge time, direct manual search SDRAM chips, can be set to 20ns can be found, i.e., set to 00. Tsrc can be obtained by Trc-Trp, the Trc total jump time required for access to another row line, in addition to the charge of Trp, Tsrc required, the Trc search, the minimum value 60ns, 40ns of the Tsrc, i.e. set to 00. Refresh Counter View SDRAM data sheet feature page, you can see the 8192 refresh cycles / 64ms, namely Refresh_period = 64ms / 8192 = 7.8us, the refresh_Couter can be calculated according to the formula as 1269.
Sequentially down to enable burst mode access (access to a plurality of memory cells at once, i.e. starting address is issued, the length, to return the value of contiguous memory locations), enabling the power down mode (power save mode by entering SCKE) enable SCLK_EN (also in energy saving considerations), BK76MAP according to 64MB that we use to select 001.
Fixed word is fixed option, you can directly select special time CL, CL is issued after the column address data can get to view the SDRAM data sheet and found that CL can be 2 or 3, press it to 2. This register is set the SDRAM mode register, a block diagram can be seen from the above SDRAM.
In summary, the output code is as follows:
s3c2440.h
----------------------------------
#ifndef __S3C2440_H
#define __S3C2440_H
#include <stdint.h>
...
//memory controller
#define BWSCON (*((volatile uint32_t*)0x48000000))
#define BANKCON0 (*((volatile uint32_t*)0x48000004))
#define BANKCON6 (*((volatile uint32_t*)0x4800001C))
#define REFRESH (*((volatile uint32_t*)0x48000024))
#define BANKSIZE (*((volatile uint32_t*)0x48000028))
#define MRSRB6 (*((volatile uint32_t*)0x4800002C))
void HardwareInitAll(void);
void Delay(uint32_t time);
#endif
s3c2440.c
------------------------
#include "s3c2440.h"
...
static void MemoryControllerInit(void)
{
BWSCON = (2<<24);
BANKCON0 = (4<<8);
BANKCON6 = (3<<15)|(0<<2)|(1<<0);
REFRESH = (1<<23) | (1269 << 0);
BANKSIZE = (1<<7) | (1<<5) | (1<<4)|(1<<0);
MRSRB6 = (2<<4);
}
void HardwareInitAll(void)
{
WatchDogDisable();
ClockDevideConfig();
ChangeModeToAsynchronous();
MPLLConfig();
MemoryControllerInit();
}
#include <stdint.h>
#include "s3c2440.h"
#include "led.h"
#include "uart.h"
int sdram_test(void)
{
volatile unsigned char *p = (volatile unsigned char *)0x30000000;
int i;
// write sdram
for (i = 0; i < 1000; i++)
p[i] = 0x55;
// read sdram
for (i = 0; i < 1000; i++)
if (p[i] != 0x55)
return -1;
return 0;
}
int main()
{
HardwareInitAll();
LedInitAll();
uint8_t led_now=kLed1;
while(1)
{
if (sdram_test() == 0)
{
SingleLedOFF(led_now++);
if(led_now > kLed3) { led_now =kLed1; }
SingleLedON(led_now);
Delay(100000);
}
}
}
Test code continuously written to the SDRAM and then read continuously determines whether the data is correct, thereby performing the lighting, if the lamp operation is successfully set.
