Notes for this article:
https://mp.weixin.qq.com/s/lVWK8xlDt7cOLi8WHYSuPg
1.SPI protocol
1.Basics
2. Introduction
3. Working principle
4.SPI data transmission steps, advantages and disadvantages
2.UART protocol
1 Introduction
2. Working principle
3.Transmission steps
4. Advantages and Disadvantages
3.I2C protocol
1 Introduction
I²C (Inter-Integrated Circuit), which should be called integrated circuit bus in Chinese, is a serial communication bus that uses a multi-master-slave architecture. It was designed by Philips in the early 1980s and facilitates motherboards, embedded systems or mobile phones. Communication with peripheral components.
Due to its simplicity, it is widely used for communication between microcontrollers and sensor arrays, displays, IoT devices, EEPROMs, etc. Using a combination of the best features of SPI and UART, you can connect multiple slaves to a single master (similar to SPI).
Also, you can have multiple masters control a single or multiple slaves. This feature is useful when you want multiple microcontrollers to log data to a single memory card or display text to a single LCD. As with UART communication, only two wires are used to transfer data between devices:
SDA (Serial Data) – This wire provides data transmission and reception capabilities for the master and slave.
SCL (Serial Clock) – This line is the clock signal line.
Like SPI, I2C is synchronous, so the output of the bits is synchronized to the sampling of the bits via a clock signal shared between the master and slave. The clock signal is always controlled by the host.
2. HOW WORKS
Using , the data is transferred in the message. Messages are broken into data frames. Each message has an address frame, which contains the binary address of the slave, and one or more data frames containing the data being transferred. The message also includes the start and stop conditions, read/write bits, and ACK/NACK bits between each data frame:
(1) Start condition (StartCondition): The SDA line is on the SCL line from High to low switching before switching from high potential to low potential.
(2) Stop Condition (StopCondition): The SDA line switches from low potential to high potential after the SCL line switches from low to high.
(3) Address Frame (AddressFrame): Each slave has a unique 7-bit or 10-bit sequence. The host can identify the slave through this sequence. If the host needs to send / To receive data, you must first send the address of the corresponding slave, and then match the address of the slave mounted on the bus.
(4) Read/Write Bit: A bit that specifies whether the host sends data to the slave (low potential) or requests the slave to send data (high potential).
(5)ACK/NACK bit (ACK/NACK Bit): In a message, each frame is followed by an acknowledgment response (ACK)/non-acknowledgment response (NACK) bit. If an address frame or data frame is successfully received, an acknowledgment bit (ACK bit) will be returned from the receiving device to the sending device.
3. ADDRESSING
There is no slave chip select interface line like SPI, so it needs another way to let the slave know that the data is being sent to it and not another slave. It requires addressing. The address frame is always the first frame after the start bit in a new message.
The master sends the address of the slave it wants to communicate with to each slave connected to it. Each slave then compares the address sent from the master with its own address. If the addresses match, it sends a low voltage ACK bit to the master. If the addresses do not match, the slave does nothing and the SDA line remains high.
4. Read/write bit (READ/WRITE BIT)
A separate bit is included at the end of the address frame to inform the slave whether the master wants to write data to it or receive data from it. If the master wants to send data to the slave, the read/write bit is low; if the master requests data from the slave, the bit is high.
5. DATA FRAME (THE DATA FRAME)
After the master detects the ACK bit from the slave, the first data frame is ready to be sent.
Data frames are always 8 bits long, and the most significant bits are sent first. Each data frame is immediately followed by an ACK/NACK bit to verify that the frame was successfully received. Before sending the next data frame, the master or slave (depending on who sends the data) must receive the ACK bit.
After all data frames have been sent, the master can send a stop condition to the slave to stop the transmission. The stop condition is that after a low to high transition on the SCL line, the voltage on the SDA line transitions from low to high and the SCL line remains high.
6. Steps of data transmission (STEPS OF I2CDATATRANSMISSION)
1. The host sends a start condition to each connected slave. Before the SCL line switches from high to low, the host switches the SDA line from high to low to trigger the start condition, that is, when SCL is high, it sends a signal to SDA. A falling edge, as shown in the figure below, pay attention to the timing direction of the arrow:
2. The master sends the 7-bit or 10-bit slave address it wants to communicate with, and the read/write bits:
3. Each slave sends the address from the master The address is compared with its own address. If the addresses match, the slave returns the ACK bit by pulling the SDA line low 1 bit. If the master's address does not match the slave's own address, the slave will leave the SDA line high (via a pull-up resistor). The slave with matching address returns the ACK bit as shown in the figure below:
4. The host sends or receives a data frame:
5. After each data frame is transmitted, the receiving device returns another ACK bit to the sender to confirm the successful receipt of the frame:
6. In order to stop data transmission, the master sends a stop condition to the slave by pulling SCL high before pulling SDA high, that is, giving SDA a rising edge when SCL is high, as shown in the figure below. Pay attention to the transmission indicated by the arrow. order:
7.SINGLE MASTER WITH MULTIPLE SLAVES
Due to the use of addressing, a single master can control multiple slaves. Using a 7-bit address theoretically provides 128 (27) unique addresses. Using 10-digit addresses is uncommon, but theoretically provides 1024 (210) unique addresses. To connect multiple slaves to a single master, connect them like below and connect the SDA and SCL lines to Vcc with 4.7K Ohm pull-up resistors:
8.MULTIPLE MASTERS WITH MULTIPLE SLAVES
Multiple masters can be connected to a single slave or to multiple slaves. In multi-master systems, problems arise when two hosts try to send or receive data over the SDA line at the same time. To solve this problem, each host needs to detect whether the SDA line is low or high before transmitting a message. If the SDA line is low, it means that another master is controlling the bus and that master should wait to send a message. If the SDA line is pulled high, it is safe to transmit messages.
To connect multiple masters to multiple slaves, connect as shown below and connect the SDA and SCL lines to Vcc using 4.7K Ohm pull-up resistors:
9. ADVANTAGES AND DISADVANTAGES OF
Advantages:
(1) Only uses two wires
(2) Supports multiple masters and multiple slaves< a i=3> (3) The ACK/NACK bit confirms that each frame was successfully transmitted (4) The hardware is not as complex as UART (5) Well known and widely used Agreement
Disadvantages:
(1)The data transfer rate is lower than SPI
(2)The size of the data frame is limited to 8 bits< a i=3> (3) The hardware required for implementation is more complex than SPI
10. Summary
(1) The bus is composed of 9-bit blocks. Start condition: When SCL is high, the falling edge of SDA transition from high to low is used as the start condition. All slaves on the bus should start paying attention:
(2) The address bit is the 7-bit data immediately following the start condition. The host wants to communicate with the slave at this address:
(3) The read-write bit is the 8th bit immediately following the 7-bit address as the read-write selection bit: This bit is used to indicate whether the host wants to read the data of the slave or write data to the slave: 1 means read; 0 means write.
(4) Synchronization bit between master and slave: 0 means ACK; 1 means NACK. 0: I am here or the data has been received. 1: No me or data not received.
(5) Data byte: The 8 bits after the address byte are the data bytes from the host or slave. As for who it comes from, it depends on the reading and writing bits. During the write cycle, the master sends data; during the read cycle, the slave sends data:
(6) Stop condition: When SCL is high level, the rising edge generated by the data line SDA jumping from low level to high level is used as the stop condition. The master notifies the slave that this communication is over.
(7) Complete bus protocol timing, as shown in the figure below:
