Simple computer system comprehensive design design report (VHDL)
1. Design purpose
Use the knowledge learned in "Digital Logic" completely and coherently, master the basic methods of using EDA tools, and pave the way for the follow-up "Computer Principles" course. Secondly, understand the application of Quartus II software, learn the basic process of designing CPU in Quartus II environment, grasp the meaning of CPU design code and the working principle of CPU, understand the transmission process of connection data between CPU and memory RAM, and learn in Quartus II environment The specific process of establishing a model machine. Integrate the content of each chapter of this course (digital logic), and deepen the understanding of the working principles and interconnections of the various modules of the computer system through the comprehensive application of knowledge. Learn the basic steps and methods of designing and debugging computers, and improve the basic skills of using software simulation tools and integrated circuits. Cultivate the ability to work independently in scientific research, and obtain practice and experience in engineering design, assembly and debugging.
2. Design content
According to the given data path, data format and instruction system, use EDA tools to design a simple computer controlled by hard-wired logic.
Data path:
Data format: The data word is represented by 8-bit binary fixed-point complement code, where the highest bit (the seventh bit) is the sign bit, and the decimal point can be regarded as the leftmost or rightmost. The range of numerical values is: -1≤X＜+1 Or -128≤X<+127.
Command system:
3. Detailed design
3.1 Overall architecture (see the last figure for enlarged view)
3.2 Specific implementation of each module
1) Instruction counter PC:
Interface design:
bus input, clock input, reset input, two control signal input, and bus output .
Function realization:
a. When the reset signal is valid, the counter is cleared;
b. When the falling edge of the clock comes, if LD_PC = '1', IN_PC = '1', it will increase by one, or LD_PC = '1', IN_PC = '0 'Realize the bus data into the counter, otherwise there is no operation;
c. The output is the current state.
2) Selector:
Interface design:
PC input, general register group A port input, general register group B port input, two-digit enable input, and bus output.
Function realization: The
function is equivalent to a multiplexer, and different inputs and outputs are selected for different enable: a.
MADD = '00', select the input and output of the PC input;
b . MADD = '01', select the general register Input and output of the input of port A of group A;
c.MADD = '10', select the input and output of the input of port B of general register group;
d.MADD = '10', output high impedance state.
3) Instruction register IR:
Interface design:
bus instruction input, clock input, enable input, instruction decomposition control signal input, bus instruction output, opcode S output, RAA, RWBA output.
Function realization: The
function is equivalent to a register (the falling edge of the clock transmits the signal to the instruction decoder), plus no signal decomposer not controlled by the clock (first extract RAA, RWAB, so that when the falling edge of the clock arrives, the general register group reads The correctness of the values).
4) Instruction decoder:
interface design:
bus instruction input terminal, reset input terminal, enable input terminal, various instruction control signal output terminals.
Function realization:
a. When the enable is valid, all kinds of command control signals are
interpreted for the incoming command code; b. When the reset signal is valid, regardless of the enable, the HALT command control signal is straight to the low level, that is, it is invalid (Used to command and control the startup operation after shutdown).
5) Controller
interface design:
enable input terminal, various command control signal input terminals, two registered signal input terminals of Cf and Zf, various control signal output terminals (LD_IR, DL, XL, etc.).
Function realization:
a. Initialize all kinds of control signals;
b. When the enable is high, that is, when it is valid, the execution stage is to assign various control signals to different command control signals and condition signals, so that the corresponding commands are executed The function block or the path is open;
c. When the enable is low, the instruction fetching stage is to change the signal that controls the value to make the instruction fetching normally.
6) General register set
Interface design:
set input, enable input, clock input, RAA and RWBA input, bus input, bus command output, general register A and B output, ABC three registers The output terminal.
Function realization:
a. When the enable is 0, the bus data is written into the three registers through RWBA selection;
b. When the enable is 1, the data in the register is output from the A port and the B port through the selection of RAA and RWBA respectively ;
C. Clear when set;
d. Display the data in the register.
7) Function generator ALU (+shift logic)
interface design:
enable input, opcode input, general register group A and B input, two shift signal input, bus output, carry Cf and The result is a 0 signal Zf output terminal.
Function realization:
a. For the incoming data from port A and port B, perform different operations according to the difference of operation codes and control signals;
b. Transmit the result from the bus, and judge whether there is a carry and whether the result is zero.
8) Switch input
interface design:
console signal INA and INP input terminal, command control signal IN_0 input terminal, eight switch signal input terminals, bus output terminal.
Function realization:
When IN_0 or INA or INP is equal to 1, the data on the switch is put into the bus.
9) Frequency divider
Interface design:
original clock input terminal, clock output terminal after frequency division.
10) Clock control switch
Interface design:
STRAT and STOP console signal input terminal, HALT command control signal input terminal, control signal output terminal.
Function realization:
According to the input signal, the signal that controls the system switch is output, and it is operated with the clock to realize the control of the system.
11) Cf, Zf register
interface design:
Cf and Zf input terminal, clock input terminal, set input terminal, Cf_1 and Zf_1 output terminal.
Function realization:
By connecting three registers in series, the register of Cf and Zf is realized, which provides conditions for the next execution stage when jumping.
12) CHP
interface design:
RAM input terminal, console signal CHP input terminal, enable input terminal, RAM value output terminal.
Function realization:
Through the control of CHP and LD_IR, the value of the corresponding memory cell in the RAM corresponding to the current PC is output.
4. Project files For
project files and reports, please refer to: https://download.csdn.net/download/hyl1181/12647130