1. The working process of the program query mode and the working principle of the query interface circuit
1. The CPU starts the input device through the I/O command, and the command device code is sent to the device selection circuit through the address line, and the device selection circuit determines the I/O device participating in the transmission.
2. When the start command and SEL signal are valid, B is set to 1 and D is set to 0. At this time, the device is started.
3. The data input by the device is saved to the data buffer register (DBR)
4. The device sends an end signal, and B is set to 0. D is set to 1, which means that the data is ready and the data can be transmitted.
5. When the CPU finds that D is 1, it means that the data has been put into the DBR, and the CPU sends the data to the general-purpose register of the CPU according to the data line, and then stores it in the main memory.
Second, the basic concept of interruption
Interruption means that during the operation of the computer, when some unexpected situation occurs and the host needs to intervene, the machine can automatically stop the running program and switch to the program to deal with the new situation, and return to the original suspended program to continue running after the processing is completed.
3. Interrupt queuing
Interrupts are queued to interrupt the execution of the current program. When there is more than one interrupt request in the same priority level, there is an interrupt priority queuing problem. When necessary, the CPU temporarily stops the execution of the current program, and then executes the program and execution process that handles the new situation.
Fourth, the formation method of the interrupt vector address
(1) Realized by the coding circuit, it is directly generated.
(2) A "displacement amount" is generated by the hardware, plus the base address stored in a register of the CPU
(3) Vector address transfer method: the corresponding fixed address code is generated by the priority encoding circuit, and the transfer instruction is stored in the address, and the transfer instruction can be transferred to the respective interrupt service program entry of the device.
5. The working principle and data transmission process of the interrupt interface circuit
Program interruption mode (the CPU realizes the parallel work with the peripheral part, that is, when the peripheral is preparing data, the CPU can still work. The I/O work is divided into two stages, self-preparation (CPU does not query) and exchange with the host information (the CPU suspends the current program to serve the I/O device), so the CPU still executes the main program normally during the equipment preparation stage, and there will be no long waiting. However, during the data transmission process, the main program still needs to be suspended. The CPU serves the device. The CPU is still located between the memory and the peripherals, so all data transmission needs to go through the CPU
6. Interrupt shielding technology
1. Interrupt masking means that during the execution of the interrupt 1 service program, it is not allowed to be disturbed by other interrupts;
2. It stands to reason that for different interrupt sources, it has an interrupt response priority, but this is determined by the hardware and cannot be modified; if you want to modify the priority of each interrupt (that is, whether it can be disturbed), you can pass the interrupt mask register (manually Set the value of this register) to achieve; this is the reason why the interrupt masking technology is proposed;
3. The specific principle of interrupt masking is: each interrupt source has an interrupt mask word (such as 16 bits); when the interrupt is responded to or the interrupt service request is executed, the mask word corresponding to the interrupt source is set to the interrupt mask register; when responding to an interrupt, the cpu will judge whether to respond to the interrupt according to the value of the mask register;
Seven, DMA control data transmission characteristics
DMA is an important feature of all modern computers, allowing hardware devices of different speeds to communicate without relying on the heavy interrupt load of the CPU. Otherwise, the CPU needs to copy each fragment's data from the source to the scratchpad, and then write them back again to the new location. During this time, the CPU is unavailable for other work.
A DMA transfer copies a memory area from one device to another. The CPU initiates the transfer. The transfer itself is performed and completed by the DMA controller.
A typical example is moving a block of external memory to faster internal memory on the chip. Instead of stalling processor work, operations like this can be rescheduled to handle other work. DMA transfers are important for high-performance embedded system algorithms and networks.