Main memory overview
The relationship between main memory and CPU
- Main memory and MDR communicate through data bus
- CPU issues read/write instructions to main memory
- MAR sends the target address of reading and writing to the main memory through the address bus
Main memory storage unit address allocation
The location of the storage unit is indicated by the unit address number , depending on the storage word length and addressing mode of the machine
Example: The word length of a certain machine is 32 bits , so it means that each storage unit (corresponding to a word) stores 32-bit binary numbers, that is, 32/8 = 4 bytes, so the range of word addressing is 4 times the byte-addressable range
Specifications of main memory
- storage
By Total Bits: 存储容量 = 存储单元个数 * 存储字长
By Total Bytes:存储容量 = 存储单元个数 * 存储字长 / 8*
Generally, it is measured by byte, 256MB -> addressable by byte, and the number of address lines is 28 bits
- storage speed
Storage speed is measured by access time and storage cycle
Access time (access time): The time required to start a memory operation to complete the operation
is divided into 2 types:
- Read time
Memory receives valid address -> produces valid output - Write time
The memory receives a valid address -> the data is successfully written to the specified memory unit
- memory bandwidth
The amount of information accessed by the memory per unit time Unit
:
- words/second
- bytes/sec
- Bits/second
Measures to increase bandwidth: - Shorten the access cycle
- Increase the storage word length
- increase memory
main memory semiconductor chip
basic structure
- CS: chip select line (determines main memory work)
- WE: read and write control line
- A0~Ax: address line
- D0~Dy: data line
decoding driver
line selection
- For a given input to the address decoder, only one line of output is valid
- Each word memory cell requires a wire
- n line n chip select signal
Coincidence law
- The memory cells are arranged in a two-dimensional matrix, with two address decoders
- A set of (X,Y) coordinates corresponds to a storage unit
- Greatly reduces the number of wires
- n line 2^n chip select signal
random access memory RAM
Static RAM (SRAM)
Dynamic RAM (DRAM)
DRAM Refresh
- Refresh cycle: generally 2ms
- Refresh a row of memory cells each time
- Centralized refresh: Refresh all capacitors within a certain period of time. During this period, DRAM is unavailable, which is called a dead zone
- Scattered refresh: After each read and write, refresh a row, no dead zone, a bit excessive refresh
- Asynchronous refresh: centralized + decentralized, refresh a row after each period of time (multiple reads and writes)
SRAM Vs DRAM
| index | DRAM | SRAM |
|---|---|---|
| storage principle | capacitance | trigger |
| Integration | high | Low |
| chip pin | few | many |
| power consumption | Small | big |
| price | Low | high |
| speed | slow | quick |
| to refresh | have | none |
ROM
Why is ROM needed? Because RAM data is volatile. ROM generally saves system information or system programs, and is read-only in the early days.
- MROM: read-only
- PROM (one-time programming): fuse training is 0, which can destroy programming at one time
- EPROM (multiple programming): N-type channel floating gate MOS circuit, if it is not turned on, it is 0
- EEPROM (Multiple Programming): Electrically Erasable, Partial Erase, Full Erase
- Flash Memory (flash memory): faster than EEPROM, with some RAM functions