Principles of Computer Composition Composition Principle (Continued from Page 4)

1. In the controller, a control signal is formed with the micro-operation signal related to what? According to an operation signal generated as a different manner, the controller can be divided into several? ( 8 )

  Instruction decoding means provide signals, status signals, and timing means provides a timing condition and the function control member is formed in an integrated feedback.

Type combinational logic, storage logic type combinational logic and storage logic bound.

2 , what is implicit instruction interrupt, the interrupt main operating instructions implicitly done what? ( 8 )

CPU after interrupt response, after some operations, turn to execute the interrupt service routine. These operations are implemented directly in hardware, called interrupt implicit instruction. Hidden interrupt instruction is not the instruction of a real command, it does not have the opcode, the instruction is an implicit break is not allowed, it is not possible special instructions for the user to use. They complete the operation are:

① save breakpoints;

② not allowed to temporary interruption;

③ leads to the interrupt service routine.

3 . The instructions and data are stored in the main memory, how to identify fetched from main memory is an instruction or data?

Solution: instructions and data are stored in main memory, which appear in binary code, as a method to distinguish between:

(1) in which the different machine cycle instruction fetch or data: Instruction fetch instruction is fetched; fetch or analyze execution cycle data is fetched.

(2) instruction fetch address or a different data sources: the instruction address from the program counter; data address from the address formed member.

4 , control input and output data transfer are there? What are the characteristics and their respective application areas? Try to compare it.

Queries the way, the program interrupt, DMA mode and channel mode

Program query is between the host and peripherals easiest way exchange of information, input and output is completely through the CPU executes the program to complete. This simple control manner, but the peripherals and the host can not work at the same time, the system efficiency is low, therefore, it applies only to the small number of peripherals on the I / O real-time less demanding processing, the CPU relatively simple operation tasks, the situation is not very busy.

Interrupt program without waiting for a query, the input and output peripherals do when ready, send an interrupt request to the host, after receiving the request to suspend execution of the original program, turn to the implementation of the external interrupt service routine request is processed, the interrupt Once processing is complete return to the original program continues. Interrupt input and output operations not only applies to external devices, but also to deal with random events occurring outside of. Since the completion of a program interruption also requires a lot of auxiliary operations, and therefore mainly suitable for medium and low-speed peripherals.

DMA mode is open direct data path between the main memory and peripherals do not need to be performed substantially CPU

Involved main memory and information transfer between peripherals, not only to ensure the CPU high efficiency, and to meet high-speed external

Set of needs. DMA mode only a simple data transfer operation, data block transfer start and end Shihai

Required CPU and the interrupt system for preprocessing and postprocessing.

The I / O channel control is DMA further development of the embodiment, provided with a passage control member in the system, each channel is linked to a number of peripheral, the host performing the I / O operation, simply start the relevant channel, the channel will execute channel program , thereby completing the I / O operations.

5 DESCRIPTION channel to complete a data transmission process mainly

A data transfer channel complete process is divided into the following three main steps:

① used in the user program instruction enters the pipe access management program, the CPU organize a program through the channel management program, and starts the channel.

Performing channel ② CPU channel program for its organization, the data input and output to complete the assigned work.

③ After the channel program to a CPU issued the interrupt request. CPU in response to the interrupt request, the second time operating system, call management program interrupt request is processed.

6 , the basic process briefly interrupt the program?

Requests, interrupt arbitration, the interrupt (interrupt instruction hidden), interrupt processing, the interrupt return

7 , Cup dedicated register and which of? What each function?

Program Counter: used to store the address of the instruction being executed or to be executed next the article refers to the address.

Instruction register : used to store the instruction fetched from the register.

Memory address registers: to save as a CPU main memory unit accessed address

Memory Data Register: for temporarily storing the read out an instruction from the main memory or a data word.

Status flag register: used to store the program status word ( PSW ).

8 , the difference Indexed addressing mode and indexed addressing mode is what?

Based addressing and Indexed Addressing in forming the effective address used by the algorithm is the same, but both of them are actually different. Generally, Indexed Addressing in an amount to provide a modified index register (variable) , and the instruction provides a reference value (constant) ; the base address base register addressing provides a reference value (fixed) , the instruction provided in the displacement amount (variable) . These two situations are different applications addressing, indexed addressing is user-oriented, access to bulk data strings, vectors and arrays; based addressing for the system, mainly for logical addresses and physical address conversion, and then to solve the positioning program in main memory address space and expansion issues. In certain mainframe, base address register can only be managed by a privileged instruction, the user's authority to operate and modify instructions.

 

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