1. The hierarchical structure of the computer
The computer system is composed of hardware and software, and if subdivided by function, it can be divided into 7 layers.
The zeroth level is the hardwired logic level, which is the core of the computer and consists of logic circuits such as gates and flip-flops.
The first level is the microprogram level. The machine language at this level is the microinstruction set, and the microprograms written by programmers with microinstructions are generally directly executed by the hardware.
The second level is the traditional machine level. The machine language at this level is the instruction set of the machine. Programs written by programmers using machine instructions can be interpreted by microprograms.
The third level is the operating system level. From the perspective of the basic functions of the operating system, on the one hand, it directly manages the hardware and software resources in traditional machines, and on the other hand, it is an extension of traditional machines.
The fourth level is the assembly language level. The machine language at this level is assembly language, and the program that completes assembly language translation is called assembly program.
The fifth level is the high-level language level. The machine language in this episode is a variety of high-level languages. Compilers are usually used to complete high-level language translation.
The sixth level is the application language level, which is specially designed to make the computer meet a certain purpose, so the language at this level is a variety of problem-oriented application languages.
Dividing the computer system into a multi-level hierarchical structure according to its function is conducive to correctly understanding the working process of the computer system and clarifying the status and role of software and hardware in the computer system.
2. The relationship between memory address and unit
Memory address (Memory address) is the number of the storage unit in the memory . Due to the large number of storage units in the memory, each storage unit needs to be assigned a memory address in order to search. A memory address is the number of a location in memory .
3. Bus and classification
(1) Bus : It is a set of public information transmission lines that can be time-shared for multiple components .
(2) 1. According to data transmission format: serial bus and parallel bus
2. According to bus function: on-chip bus, system bus, communication bus
3. According to timing control mode: synchronous bus, asynchronous bus
4. Bus characteristics and performance indicators
(1) Bus characteristics:
- Mechanical characteristics: size, shape, number of pins, arrangement order
- Electrical characteristics: transmission direction and effective level range
- Functional characteristics: the function of each transmission line (address, data, control)
- Temporal characteristics: the timing relationship of the signal
(2) Bus performance index
1. The transmission cycle of the bus (bus cycle)
The time required for a bus operation (including application phase, addressing phase, transmission phase and end phase) usually consists of several bus clock cycles.
2. Bus clock cycle
That is, the clock cycle of the machine. The computer has a unified clock to control the various components of the entire computer, and the bus is also controlled by this clock.
3. The working frequency of the bus
The frequency of various operations on the bus, which is the reciprocal of the bus cycle. If the bus cycle = N clock cycles, then the operating frequency of the bus = clock frequency / N. In fact, it refers to sending data several times in one second.
4. The clock frequency of the bus
That is, the clock frequency of the machine, which is the reciprocal of the clock period. If the clock period is T, the clock frequency is 1/T. It actually refers to how many clock cycles there are in one second.
5. Bus width
Also known as the bus bit width, it is the number of data bits that can be transmitted on the bus at the same time. It usually refers to the number of data buses, such as 32 called 32-bit (bit) buses.
Bus bandwidth = bus operating frequency × bus width (bit/s) = bus operating frequency × (bus width/8) (B/s)
6. Bus bandwidth
It can be understood as the data transmission rate of the bus, that is, the number of bits of data that can be transmitted on the bus per unit time, usually measured by the number of bytes of information transmitted per second, and the unit can be expressed in bytes per second (B/s).
7. Bus multiplexing
Bus multiplexing means that a signal line transmits different information at different times. More information can be transmitted using fewer wires, saving space and cost.
8. Number of signal lines
The sum of the three bus numbers of address bus, data bus and control bus is called the number of signal lines.
Five, bus structure: single bus structure, double bus structure and three bus structure
(1) Single bus structure: It is a group of buses connecting the major functional components of the entire computer system, and all information transmission between the major components passes through this group of buses.
(2) The dual-bus structure has two buses, one is the main memory bus, which is used for data transmission between the CPU, main memory and channels; the other is the I/O bus, which is used for communication between multiple external devices and channels. data transmission.
(3) The three-bus structure is to use three independent buses between the components of the computer system to form an information path. These three buses are the main memory bus, the I/O bus and the direct memory access DMA bus.
6. Bus connection mode: serial transmission, parallel transmission and time-sharing transmission
1. Serial transmission
When information is transmitted serially, there is only one transmission line and it is transmitted in pulses.
In serial transmission, the pulse signals representing all binary bits (bits) of a digital are transmitted in sequence, one bit at a time, usually the first pulse signal represents the least significant bit of the digital, and the last pulse signal represents the digital most significant bit.
During serial transmission, the transmitted data needs to undergo parallel-to-serial conversion in the sending part, which is called disassembly; while the serial-to-parallel conversion is required in the receiving part, which is called assembly.
2. Parallel transmission
When transmitting binary information in parallel, a separate transmission line is required for each data bit. The number of binary bits that the information consists of requires as many transmission lines, so that the binary number "0" or "1" is transmitted on different lines at the same time.
Parallel transmission generally adopts electric potential transmission. Parallel data transfers are much faster than serial data transfers because all bits are transferred at the same time.
3. Time-sharing transmission
Two concepts of time-sharing transmission:
• One is to use the bus multiplexing method, where both address information and data information are transmitted on a certain transmission line. For this reason, time slices must be divided so that the tasks of transmitting addresses and transmitting data can be completed in different time intervals.
•Another concept is that the components sharing the bus time-share the bus.
7. Bus control: chain query mode, counting timing query mode and independent request mode
(1) The chain query method only needs 1 bus request line (BR), 1 bus busy line (BS) and 1 bus consent line (BG). The BG line is like a chain, connecting all the devices in series. The priority of the device is fixed, the structure is simple, and it is easy to expand the device, but it is very sensitive to circuit failure. Once the interface circuit of the i-th device is faulty, the i-th device after equipment cannot work.
(2) The bus request (BR) and busy (BS) lines of the counter timing query mode are shared by each device, but lbN (N is the number of devices) device address lines are needed to realize the query. The priority of the equipment can not be fixed, the control is more complex than the chain query, and the circuit fault is not as sensitive as the chain query.
(3) The number of control lines in the independent request mode is large, and N devices share N bus request lines and N bus consent lines, and the bus arbitration line is more complicated. But the response time is fast, and the sequence control of device priority is flexible, which can be fixed in advance, or the priority sequence can be changed through the program, and the request of certain devices can also be blocked when necessary.
Eight, bus communication: synchronous communication and asynchronous communication
(1) Synchronous communication: The information transmission between components is synchronized by the system time scale with fixed bandwidth and fixed distance. The transmission rate of information is high, and it is less affected by the length of the bus. The time lag on the bus may cause synchronization errors, and the interference signal on the clock may easily cause missynchronization (2) Asynchronous
communication: because the I/O bus is generally different The speed is shared by many I/O devices, so it is easy to use asynchronous communication. Asynchronous communication is further divided into one-way control and request/reply two-way control.