Table of contents

This chapter will carry out the whole process of FPGA DSP development, including the following steps

Ok, let's start~

1. Actual development process

1.1 matlab input signal

1.1.1 matlab input signal code

clc;clear all;close all;
%--------------------------------------------------------------------------
%%  FIR 滤波器输入信号生成
%--------------------------------------------------------------------------

%% 系统参数
N = 1024;%采样点数
Fs = 10000;
Ts = 1/Fs;

%% 输入信号生成，由100Hz和2000Hz正弦信号合成
A = 3;
t = (0:N-1)*Ts;
ft_0 = 100;
vi_0 = zeros(1,N);
ft_1 = 2000;
vi_1 = zeros(1,N);
vi = zeros(1,N);

for n = 1:N
    vi_0(n) = A*sin(2*pi*ft_0*t(n));
    vi_1(n) = A*sin(2*pi*ft_1*t(n));
    vi(n) = vi_0(n) + vi_1(n);%混频
end

%% 信号图像输出
figure(1)
subplot(3,1,1)
plot(t,vi_0,'k');
subplot(3,1,2)
plot(t,vi_1,'k');
subplot(3,1,3)
plot(t,vi,'k');

Fre0 = abs(fft(vi_0)); %快速傅里叶变换的幅值
Fre1 = abs(fft(vi_1));
Fre = abs(fft(vi));
f = (0:N-1)*Fs/N;%频率离散化

figure(2)
subplot(3,1,1)
plot(f,Fre0);
xlabel('Frequency'); 
ylabel('Amplitude'); 
subplot(3,1,2)
plot(f,Fre1);
xlabel('Frequency'); 
ylabel('Amplitude'); 
subplot(3,1,3)
plot(f,Fre);
xlabel('Frequency'); 
ylabel('Amplitude'); 

%fftshift()调整0频位置
figure(3);
f1=(0:N-1)*Fs/N-Fs/2 ;%频率范围-5000Hz-5000Hz, 1024个采样点
y0=abs(fftshift(fft(vi_0)));
subplot(3,1,1)
plot(f1,y0);
xlabel('Frequency'); 
ylabel('Amplitude'); 
y1=abs(fftshift(fft(vi_1)));
subplot(3,1,2)
plot(f1,y1);
xlabel('Frequency'); 
ylabel('Amplitude');
y=abs(fftshift(fft(vi)));
subplot(3,1,3)
plot(f1,y);
xlabel('Frequency'); 
ylabel('Amplitude');

1.1.2 Output image

Time Domain Plot of Three Signals	Spectrogram of three signals	The spectrogram after adjusting the 0 frequency

1.2 Use of System Generator

1.2.1 Basic use

Note: Our matlab must be opened through the system generator of xilinx

You can refer to the System Generator tutorial to assist us in using the software. The development steps follow the video tutorial below

0 Platform_哔哩哔哩_bilibili https://www.bilibili.com/video/BV1K54y1v76u?p=2&vd_source=71acea6682c8121539b919e1e8ca93ef

First we need to add the System Generator module and set the system hardware parameters

Next place our input signal block

Special reminder: If we want to input the parameters such as the mixing signal generated by matlab in 1.1 to our system generator module, we need to first run the .m file to generate the required variables, and then add the corresponding input parameters in the system generator module. And preferably Simulin files and matlab files in one parent folder

The counter counter and the memory rom module constitute the input of the whole system, input the vi mixing waveform generated by our matlab, a total of 1024 sampling data points.

1.2.2 FIR IP core

Note: We also need a matlab FDATool module (the one above FIR Complier7.2 in the figure), which provides the FIR filter with the filter tap coefficients at the required order.

Click the FIR Complier7.2 module, enter xlfda_numerator('FDATool') , and after turning the two into a subsystem in chapter 1.2.3, you can link FDATool and FIR Complier on a Simulink panel

For other configurations, see video 8:20

Issue 4 - FIR Filter Call Process - Development Notes of FPGA-Based Digital Signal Processing System

1.2.3 FIR filter design

Completed by FDATool, the filter design requirements: the input sampling rate is 10KHz, the effective signal is 0.1KHz, and the high-frequency signal is filtered out at 2KHz