Principles of Computer Organization Final Exam Questions and Answers
1. Multiple choice questions
1. A complete computer system should include ______. D.
A. Calculator, memory and controller B. Peripheral devices and host
C. Host and utilities D. Supporting hardware and software systems
2. The memory system in a computer system refers to ______. D.
A. RAM memory B. ROM memory
C. main memory D. main memory and external memory
3. The basic characteristic of the working method of von Neumann machine is ______. B
A. Multiple instruction stream single data stream B. Access and execute instructions sequentially by address
C. Stack operation D. Memory selects address by internal
4. Which of the following statements is incorrect is ______. D.
A. Any operation that can be implemented by software can also be implemented by hardware
B. Firmware is similar to software in function and hardware in form
C. In the hierarchical structure of the computer system, the microprogram level belongs to the hardware level, and the other four levels are all software levels
D. Machines for high-level languages are fully achievable
5. The smallest number among the following numbers is ______. C
A. (101001)2 B. (52)8 C. (101001)BCD D. (233)16
6. The largest number among the following numbers is ______. B
A. (10010101)2 B. (227)8 C. (143)5 D. (96)16
7. In the machine, the representation of zero of ______ is unique. B
A. Original code B. Complementary code C. Inverse code D. Original code and inverse code
9. For 8-bit binary numbers, the correct one of the following statements is ______. B
A. The complement of -127 is 10000000 B. The complement of -127 is equal to the shift of 0 B
C. The frame shift of +1 is equal to the complement of –127 D. The complement of 0 is equal to the complement of –1
9. An 8-bit binary integer is expressed in complement code and consists of 3 "1"s and 5 "0", the minimum value is ______. B
A. –127 B. –32 C. –125 D. –3
10. The purpose of using complement arithmetic in computer systems is to ______. C
A. Consistent with the manual calculation method B. Improve the calculation speed
C. Simplify the design of the computer D. Improve the accuracy of calculation
11. If the true value of a certain number x is –0.1010, and the number is expressed as 1.0110 in the computer, then the encoding method used for the number is ______ code. B
A. Original B. Complement C. Reverse D. Shift
12. For two types of floating-point numbers with the same length but different formats, assuming that the former has a long stage and a short mantissa, and the latter has a short stage and a long mantissa, and other regulations are the same, the range and precision of the numbers they can represent are ______. B
A. The range and precision of the numbers that can be represented by the two are the same B. The range of numbers that can be represented by the former is large but the precision is low
C. The latter can represent a large range of numbers with high precision D. The former can represent a large range of numbers with high precision
13. The word length of a certain machine is 32 bits, which is represented by fixed-point decimals. The sign bit is 1 bit, and the mantissa is 31 bits. The maximum positive decimal that can be expressed is ______, and the minimum negative decimal is ______. D.
A. +(231–1) B. –(1–2-32)
C. +(1–2-31)≈+1 D. –(1–2-31)≈–1
14. Although the arithmetic unit is composed of many parts, the core part is ______. B
A. Data bus B. Arithmetic logic operation unit
C. Multiplexer D. General purpose register
15. In the fixed-point binary arithmetic unit, the subtraction operation is generally realized by ______. D.
A. Binary subtractor for original code operation B. Binary subtractor for complement code operation
C. Decimal adder for complement operation D. Binary adder for complement operation
16. In the fixed-point arithmetic unit, no matter whether double sign bit or single sign bit is used, there must be ______, which is generally realized by ______. C
A. Decoding circuit, NAND gate B. Encoding circuit, NOR gate
C. Overflow judgment circuit, XOR gate D. Shift circuit, NOR gate
17. Which of the following statements is correct is ______. D.
A. Addition and subtraction using deformed complement can avoid overflow
B. Only fixed-point arithmetic may overflow, and floating-point arithmetic will not produce overflow
C. Only operations with signed numbers may cause overflow
D. Adding two positive numbers may cause overflow
18. The reason for overflow in fixed-point arithmetic is ______. C
A. During the operation, the highest bit generates carry or borrow
B. The operands participating in the operation exceed the representation range of the machine
C. The operand of the result of the operation exceeds the representation range of the machine
D. The number of bits in the register is too small, and the least significant bit has to be discarded
19. Underflow refers to ______. A
A. The absolute value of the operation result is less than the minimum absolute value that the machine can represent
B. The result of the operation is less than the smallest negative number that the machine can represent
C. The result of the operation is less than the smallest positive number that the machine can represent
D. Errors generated by the least significant bit of the operation result
20. The storage unit refers to ________. B
A. A storage element storing a binary information bit B. A collection of all storage elements storing a machine word
C. A set of all storage elements storing one byte D. A set of all storage elements storing two bytes
21. Compared with external memory, internal memory is characterized by ________. C
A. Large capacity, fast speed, low cost B. Large capacity, slow speed, high cost
C. Small capacity, fast speed, high cost D. Small capacity, fast speed, low cost
22. A computer has a word length of 16 bits and a memory capacity of 64KB. If it is addressed by word, its address range is ________. B
A. 64K B. 32K C. 64KB D. 32KB
23. A certain DRAM chip has a storage capacity of 512K×8 bits, and the number of address lines and data lines of this chip is _______. C
A. 8，512 B. 512，8 C. 18，8 D. 19，8
24. The word length of a certain computer is 32 bits, and its storage capacity is 4MB. If it is addressed by word, its addressing range is ________. D.
A. 1M B. 4MB C. 4M D. 1MB
25. The purpose of adding Cache between main memory and CPU is ________. A
A. Solve the speed matching problem between CPU and main memory
B. Increase the capacity of the main memory
C. Expand the number of general-purpose registers in the CPU
D. Expand both the main memory capacity and the number of CPU general-purpose registers
26. EPROM refers to ________. D.
A. Read-only memory B. Random access memory
C. Programmable read-only memory D. Erasable programmable read-only memory
27. In the register indirect addressing mode, the operand is in __________. B
A. General purpose registers B. Memory unit C. Program counter D. Stack
28. The extended opcode is __________. D.
A. The code for the auxiliary operation field outside the opcode field
B. The code used to classify the instruction in the opcode field
C. Opcodes in Instruction Formats
D. An instruction optimization technology, instructions with different address numbers can have different opcode lengths
29. The main purpose of using different addressing modes in the instruction system is __________. B
A. Implement Stored Program and Program Control
B. Shorten instruction length, expand addressing space, and improve programming flexibility
C. Can directly access external memory
D. Provide the possibility of expanding the opcode and reduce the difficulty of instruction decoding
30. In order to complete the arithmetic operation of two numbers in a single address instruction, except for one operand specified by the address code, the other number often uses __________. C
A. Stack addressing mode B. Immediate addressing mode
C. Implicit addressing mode D. Indirect addressing mode
31. The addressing mode of the operand in a register is called __________ addressing. C
A. direct B. indirect C. register D. register indirect
32. In the register indirect addressing mode, the operand is in __________. B
A. General purpose registers B. Main memory unit C. Program counter D. Stack
33. In the indexed addressing mode, the effective address of the operand is equal to __________. C
A. The content of the base value register plus the formal address (displacement) B. The content of the stack pointer plus the formal address
C. The content of the index register plus the formal address D. The content of the program counter plus the formal address
34. The function of program control instructions is __________. D.
A. Perform arithmetic and logic operations B. Perform data transfer between main memory and CPU
C. Perform data transfer between the CPU and I/O devices D. Change the order of program execution
35. The synchronous control method is __________. C
A. Only applicable to CPU control mode B. Only applicable to peripheral device control mode
C. A method controlled by a unified timing signal D. A method in which all instructions are executed at the same time
36. The asynchronous control method is often used in __________ as its main control method. A
A. When accessing the main memory and peripherals in a computer with a single-bus structure B. During CPU control of a microcomputer
C. In the CPU controlled by combinatorial logic D. In the microprogram controller
37. In a microcycle __________. D.
A. Only one micro-operation can be performed
B. Can perform multiple micro-operations, but they must be operated in parallel
C. Can perform multiple micro-operations sequentially
D. Only mutually exclusive operations can be performed
38. Instruction cycle refers to __________. C
A. The time it takes for the CPU to fetch an instruction from main memory
B. The time it takes for the CPU to execute an instruction
C. CPU fetches an instruction from main memory plus the time to execute this instruction
D. Clock cycle time
39. The register that tracks the successor address of an instruction in the CPU is __________. B
A. Main memory address register B. Program counter
C. Instruction register D. Status register
40. The central processing unit refers to __________. C
A. Calculator B. Controller
C. Arithmetic unit and controller D. Arithmetic unit, controller and main memory
41. The minimum unit of time for computer operation is __________. A
A. Clock cycles B. Instruction cycles C. CPU cycles D. Peripherals
42. In a microprogram controller, the relationship between machine instructions and microinstructions is __________. B
A. Each machine instruction is executed by a microinstruction
B. Each machine instruction is interpreted and executed by a microprogram compiled with microinstructions
C. A program consisting of a segment of machine instructions can be executed by a single microinstruction
D. A microinstruction consists of several machine instructions
43. In order to determine the address of the next microinstruction, the judgment method is usually used, and the basic idea is __________. C
A. Use the program counter PC to generate the continuation microinstruction address
B. Use microprogram counter μPC to generate subsequent microinstruction address
C. The subsequent microinstruction address is controlled by the designer's designation or the designer's designation through the microinstruction control field.
D. Use a special field in the instruction to control the generation of subsequent microinstruction addresses
44. As far as the encoding method of micro-commands is concerned, if the number of micro-operation commands has been determined, then __________. B
A. The direct representation has a shorter microinstruction word size than the coded representation
B. Coded representation has a shorter microinstruction word size than direct representation
C. The coded representation and the direct representation have the same microinstruction word length
D. The relationship between the word length of the microinstructions in the coded representation and the direct representation is uncertain
45. The correct one of the following statements is __________. B
A. Compared with the hard-wired control method, the micro-program control method can make the execution speed of the instruction faster
B. If the micro-program control method is adopted, the PC can be replaced by μPC
C. Control memory can be implemented with mask ROM, EPROM or flash memory
D. The instruction cycle is also called the CPU cycle
46. The function of the address line in the system bus is . C
A. Used to select the main memory unit
B. Devices Used to Select Information Transferred
C. Used to specify the address of the main memory unit and I/O device interface circuit
D. Used to transfer main memory physical address and logical address
47. The width of the data bus is defined by the bus. A
A. Physical characteristics B. Functional characteristics C. Electrical characteristics D. Time characteristics
48. In a stand-alone system, the bus system of a computer with a multi-bus structure is generally composed of. A
A. System bus, memory bus, and I/O bus B. Data bus, address bus, and control bus
C. Internal bus, system bus and I/O bus D. ISA bus, VESA bus and PCI bus
49. Which of the following statements is incorrect . A
A. The bus structure transmission method can increase the data transmission speed
B. Compared with the independent request method, the chain query method is more sensitive to the failure of the circuit
C. PCI bus adopts synchronous timing protocol and centralized arbitration strategy
D. The bandwidth of the bus is the highest transmission rate that the bus itself can achieve
50. When an interrupt occurs, the program counter PC is updated by hardware instead of software, mainly for ________. C
A. Can enter the interrupt handler and return to the source program correctly B. Save content
C. Increase the speed of the processor D. Make the interrupt handler easy to address and less prone to errors
51. Among the four items of I/O device, data channel, clock and software, the source of interrupt may be ________. D.
A. I/O devices B. I/O devices and data channels
C. I/O devices, data channels, and clocks D. I/O devices, data channels, clocks, and software
52. The difference between a single-level interrupt and a multi-level interrupt is ________. A
A. Single-level interrupts can only implement single interrupts, while multi-level interrupts can implement multiple interrupts
B. The hardware structure of a single-level interrupt is a one-dimensional interrupt, while the hardware structure of a multi-level interrupt is a two-dimensional interrupt
C. A single-level interrupt processor is connected to its external device system through only one external interrupt request line; while a multi-level interrupt, each I/O device has a dedicated external interrupt request line
53. In a single-level interrupt system, once the CPU responds to the interrupt, it immediately turns off the ________ flag to prevent other interrupt sources of the same level from generating another interrupt to interfere before the end of the interrupt service. A
A. Interrupt enable B. Interrupt request C. Interrupt mask
54. In order to facilitate multi-level interruption, the most effective way to save on-site information is to use ________. B
A. General register B. Stack C. Storage D. External memory
55. In order to realize the parallel work of CPU and external devices, the basic hardware that must be introduced is ________. A
A. Buffer B. Channel C. Clock D. Associative Register
56. The interrupt enable trigger is used to ________. D.
A. Indicates whether the peripheral has raised an interrupt request B. Whether the CPU has responded to the interrupt request
C. Whether the CPU is processing interrupts D. Open or close maskable hardware interrupts
57. When using DMA to transfer data, each time a piece of data is transferred will take up a ________ time. C
A. instruction cycle B. machine cycle C. store cycle D. bus cycle
58. The cycle embezzlement method is often used in the input/output of the ________ method. A
A. DMA B. Interrupt C. Program transfer D. Channel
59. The channel is an important I/O method, and the channel suitable for connecting a large number of terminals and printers is ________. C
A. Array mux B. Select lane C. Byte mux
60. The characteristic that magnetic surface memory does not have is ______. C
A. High storage density B. Can be saved offline C. Fast speed D. Large capacity
61. The external equipment of the computer refers to ______. D.
A. Input/Output Devices B. External Storage Devices
C. Telecommunications equipment D. Other equipment except CPU and memory
62. In the microcomputer system, the external devices are connected to the system bus of the main board through ______. B
A. accumulator B. device controller C. counter D. register
2. Short answer questions
1. What are the basic characteristics of a von Neumann computer?
Answer: The basic idea of the von Neumann principle is:
• Represents data and instructions in binary form. Instructions consist of opcodes and address codes.
• Store programs and data in the memory, so that the computer can take out instructions from the memory to execute when it is working, and automatically complete the calculation task. This is the concept of "stored program" and "program control" (referred to as stored program control).
• The execution of instructions is sequential, that is, the instructions are generally executed in the order they are stored in the memory, and the program branch is realized by the transfer instruction.
• A computer is composed of five basic components: memory, arithmetic unit, controller, input device and output device, and the basic functions of the five parts are specified.
The basic characteristics of von Neumann computers can also be highly summarized by "stored program" and "program control".
2. What are the components of computer hardware, and what are the functions of each component?
Answer: The hardware system of a computer is composed of tangible electronic devices, etc., including arithmetic units, memory, controllers, input and output devices, and bus systems. The bus is divided into a data bus, an address bus, and a control bus, and its structure includes a single-bus structure, a double-bus structure, and a multi-bus structure. Memory (Memory) is a component used to store data and programs; an arithmetic unit is a component that performs calculations on information; a controller is the control core of the entire computer. Its main function is to read instructions, translate instruction codes, and send control signals to various parts of the computer in order to execute instructions; the input device can transform data and programs into information that can be recognized and accepted by the computer, and sequentially convert them They are sent to the memory; the output device sends the results of computer processing in a form acceptable to people or other machines.
3. What is a bus? What kinds of structures are there to form a computer with a bus?
Answer: The bus (Bus) is the common channel used to transmit information in the computer, and it is a set of information transmission connection lines serving multiple components. According to the connection mode of the bus, the computer structure can be divided into single-bus structure, dual-bus structure and multi-bus structure (see Chapter 7 for details).
4. What are hardware, software and firmware? What is the logical equivalence of software and hardware? In what sense are software and hardware not equivalent?
Answer: Computer hardware (Hardware) refers to the collection of all physical components that make up a computer. Usually, these components are composed of physical components such as circuits (electronic components) and machinery. Computer software (Software) refers to the programs and data needed to make the computer work, as well as the text descriptions and diagrams related to these programs and data, where the text descriptions and diagrams are also called documents. Firmware (Firmware) is an entity between traditional software and hardware. It is similar to software in function, but it is hardware in form. Microprogram is an important form of combining computer hardware and software.
The logical equivalent meaning of software and hardware:
(1) Any operation completed by software can also be directly implemented by hardware
(2) Any instruction executed by hardware can also be completed by software
Software and hardware are not equivalent in a physical sense.
5. What levels are computer systems divided into according to programming languages?
Answer: A computer system is a multi-level hierarchical structure composed of hardware and software. It is usually composed of microprogram level, general machine level, operating system level, assembly language level, and high-level language level. Program design can be created at each level. , and get the support of the subordinates.
6. Explain the following concepts: ALU, CPU, host and word size.
Answer: Arithmetic Logic Unit (ALU: Arithmetic Logic Unit) is the core component of the calculator, and its function is to complete arithmetic and logic operations. "Central Processing Unit" (CPU: Central Processing Unit) includes arithmetic units and controllers, and is the central component of computer information processing. Memory, arithmetic unit and controller play a major role in information processing operations and are the main part of computer hardware, often referred to as "host". The word length determines the computing precision of the computer, the length of the instruction word, the length of the storage unit, etc., and can be 8/16/32/64/128 bits (bit), etc.
7. What are the commonly used computer performance indicators?
Answer: Evaluating computer performance is a complex issue. In the early days, it was limited to three major indicators: word length, computing speed, and storage capacity. The factors to be considered at present are as follows.
(1) Main frequency
The main frequency determines the operating speed of the computer to a large extent, and its unit is megahertz (MHz).
(2) word length
The word length determines the computing precision of the computer, the length of the instruction word, the length of the storage unit, etc., and can be 8/16/32/64/128 bits (bit).
(3) Operation speed
The early method of measuring the speed of computer operations was the number of addition instructions executed per second, and now the equivalent speed is usually used.
(4) Storage capacity
Computers with words as the unit often express the storage capacity by multiplying the number of words by the word length.
(5) Reliability
Whether the system runs stably is very important, and it is often measured by mean time between failures (MTBF).
(6) Maintainability
System maintainability refers to whether the system can be restored as soon as possible when a fault occurs. It can be expressed by mean time to repair (MTRF), which refers to the average time required from the occurrence of a fault to the repair of the machine.
(7) Availability
Refers to the efficiency of computer use.
(8) Compatibility
Compatibility is a broad concept, which refers to the performance of a device or program that can be used in multiple systems. Compatibility enables the inheritance and development of machine resources, which is conducive to the promotion and popularization of computers.
8. What is the meaning of multimedia?
Answer: Multimedia technology refers to the technology that can acquire, process, edit, store and display two or more media of different information types at the same time. The form of computer information can be text, sound, graphics and images, etc.
9. Briefly describe the hierarchical structure of the computer and explain the main characteristics of each level.
Answer: A modern computer system is a complex of hardware and software, which can be regarded as a multi-level hierarchical structure divided by function.
Level 0 is an entity composed of hardware.
Level 1 is the microprogram level. The machine language at this level is the microinstruction set, and the microprograms written by programmers with microinstructions are generally directly executed by the hardware.
Level 2 is the traditional machine level. The machine language at this level is the instruction set of the machine, and programs written by programmers using machine instructions can be interpreted by microprograms.
Level 3 OS level. From the perspective of the basic functions of the operating system, on the one hand, it directly manages the hardware and software resources in traditional machines, and on the other hand, it is an extension of traditional machines.
Level 4 is the assembly language level. The machine language at this level is assembly language, and the program that completes assembly language translation is called an assembler.
Level 5 is the advanced language level. This level of machine language is a variety of high-level languages, and compilers are usually used to complete high-level language translation.
Level 6 is the applied language level. This level is specially designed to make the computer meet a certain purpose, so this level of language is a variety of problem-oriented application languages.
10. What are the main technical indicators of the computer system?
The main technical indicators of the computer system are: machine word length, data path width, main memory capacity and computing speed, etc.
The machine word length refers to the basic number of digits involved in the operation, which is determined by the number of adders and registers.
The data path width refers to the number of bits that the data bus can transmit information in parallel at one time.
The main memory capacity refers to all the information that the main memory can store.
The computing speed is related to many factors such as the main frequency of the machine, what kind of operation is performed, and the speed of the main memory itself.
11. Try to calculate how many bytes a Chinese character font using 32×32 dot matrix fonts occupies? How much storage capacity is required to store 6763 Chinese character libraries of 16×16 dot matrix and 24×24 dot matrix fonts?
Answer: 128B 216416B 486936B
12. What are the coding rules of the Hamming check code?
Answer: If the highest bit number of the Hamming code is m and the lowest bit number is 1, that is, HmHm-1...H2H1, then the encoding rule of the Hamming code is:
(1) The sum of the parity bit and the data bit is m, and each parity bit Pi is divided into the position of the bit number 2i-1 in the Hamming code, and the rest of the bits are data bits, and they are bit by bit from low to high Each data bit is assigned in sequential order.
(2) Each bit code Hi (including data bits and check digits) of the Hamming code is checked by multiple check bits, and the relationship is that each bit number to be checked must be equal to the school checks that check it. The sum of the digit numbers of the check digits.
13. Briefly describe the error correction principle of CRC code.
Answer: CRC code is a code with strong error correction ability. When checking, divide the CRC code polynomial and the generator polynomial G(X), if the remainder is 0, it indicates that the data is correct; when the remainder is not 0, it indicates that the data is wrong. As long as the appropriate generator polynomial G(X) is selected, the corresponding relationship between the remainder and the error bit position of the CRC code is certain, so the remainder can be used as a basis to judge the error position and correct the error code.
14. What parts does the arithmetic unit consist of?
Answer: The basic structure of the calculator should include the following parts:
(1) The component ALU that can realize arithmetic and logic operation functions;
(2) A general-purpose register group storing the information to be processed or the processed result information;
(3) Components that control data input according to operation requirements: multi-way switch or data latch;
(4) Components that control data output according to operation requirements: output shift and multiplexer;
(5) The bus for information transmission between the calculator and other components, as well as the bus receiver and transmitter; the bus receiver and transmitter are usually composed of three-state gates.
15. What performance indicators does the main memory have? What do they mean?
Answer: The performance index of the memory is the main basis for designing, using and improving the memory. The performance index of the memory is also called the memory parameter.
(1) Storage capacity refers to the total amount of binary information that a fully functional memory can hold, that is, how many bits of binary information codes can be stored.
(2) Memory speed: memory access time and memory access cycle
(3) Data transfer rate: The maximum amount of information that can be written into or retrieved from the memory per unit time is called the data transfer rate or memory transfer bandwidth bM
(4) Reliability The reliability of the memory refers to the condition that the memory has no faults within the specified time, and is generally measured by the mean time between failures (MTBF).
(5) Price: Also known as cost, it is an important indicator to measure the economic performance of main memory.
16. What are the basic components of main memory? What is the main function of each part?
Answer: The basic composition of the main memory:
(1) A storage body that stores information. Generally, it is a storage array in which all basic storage units are arranged according to certain rules. Banks are the heart of memory.
(2) The addressing mechanism of information, that is, the address selection mechanism for reading and writing information. This includes: Address Register (MAR) and Address Decoder. The address decoder completes address decoding, and the address register has an address buffer function.
(3) Memory data register MDR. It can play the role of data buffer in data transmission.
(4) The energy required to write information, that is, write lines, write drives, etc.
(5) Energy sources and sense amplifiers required for reading, that is, read lines, read drivers and sense amplifiers.
(6) Memory control unit. Including main memory timing lines, clock pulse lines, read logic control lines, write or rewrite logic control lines, and timing refresh lines of dynamic memory, etc. These lines are collectively called memory control components.
17. What are the characteristics of static MOS storage unit and dynamic MOS storage unit?
Answer: In MOS semiconductor memory, according to the principle of storing information mechanism, it is divided into static MOS memory (SRAM) and dynamic MOS memory (DRAM). The former uses a bistable flip-flop to store information. will be lost, the latter uses MOS capacitors to store charges to save information, and the capacitor needs to be charged continuously to keep the information when in use.
18. What is refresh? Why refresh? What are the common refresh methods?
Answer: For dynamic memory, it is necessary to charge the storage capacitors of all basic storage elements at regular intervals (usually 2ms), which is called RAM refresh, and 2ms is the refresh interval. Due to the leakage of the charge stored in the information, the charge of the dynamic memory cannot be continuously replenished by the power supply through the load tube like the static memory circuit. After a long time, the information will be lost, so it must be refreshed. There are two commonly used refresh methods: centralized refresh and distributed refresh.
19. Briefly explain what are the measures to improve the memory speed?
Answer: Cache memory, multi-body interleaved memory.
20. What are the characteristics of Cache?
Answer: Cache has the following characteristics:
(1) Located between the CPU and main memory, it is the highest level in the memory hierarchy.
(2) The capacity is smaller than the main memory, generally several KB to several MB at present.
(3) The speed is generally 5 to 10 times faster than the main memory, and is usually composed of bipolar transistors or SRAMs with high storage speed.
(4) Its capacity is a partial copy of main memory.
(5) It can be used to store instructions and also can be used to store data.
(6) The functions of fast storage are all realized by hardware and transparent to programmers.
21. How to distinguish between memory and register? The two are the same thing, right?
Answer: Memory and registers are not the same thing. The memory is outside the CPU and is specially used to store programs and data, and the speed of accessing the memory is relatively slow. Registers are part of the CPU, and access to registers is fast.
22. What is the main function of memory? Why divide the storage system into several different layers? What are the main levels?
Answer: The main function of memory is to save programs and data. A storage system is a system in which several memories with different capacities, speeds and prices are connected by means of hardware, software, and a combination of hardware and software. The purpose of dividing the storage system into several different levels is to solve the contradiction between storage capacity, access speed and price. The three-level storage system composed of cache memory, main memory and auxiliary memory can be divided into two levels, among which the cache and main memory are called Cache-main memory storage level (Cache storage system); the main memory and auxiliary memory Called the primary storage - secondary storage storage hierarchy (virtual storage system).
23. Explain the difference between storage cycle and access time.
Answer: The access cycle refers to the total time required for a complete read and write operation of the main memory, that is, the shortest time required between two consecutive memory access operations. Access time refers to the time elapsed from the initiation of a memory operation to the completion of the operation. The access period must be greater than the access time.
24. What are the guidelines for instruction format design?
Answer: The instruction format that a computer chooses involves many factors. It is generally required that the word length of the instruction be shorter to obtain advantages in time and space. But the instruction must also have sufficient length to facilitate the increase of information volume. Furthermore, the instruction word length should generally be an integer multiple of the machine character length for storage system management. In addition, the design of the instruction format is also related to how to select the number of bits of the operand address in the instruction.
25. Instructions are flexible and changeable, in which aspects?
Answer: Instructions are flexible and changeable, mainly reflected in the following aspects: various instruction formats; rich addressing methods; various instruction types; the number of operation codes can change with the number of address codes (extended operation code mode) ; Command length variable, etc.
26. Try to compare the similarities and differences between base addressing and indexed addressing.
Answer: The base addressing mode and the indexed addressing mode are similar in form. However, users can use the indexed addressing mode to write programs, and in the base addressing mode, the user program has no right to operate and modify the base register, and the system software management control program uses privileged instructions to manage it. Furthermore, the base addressing method is mainly used to solve problems such as locating the program in the memory and expanding the addressing space.
27. What is a stack? What are the characteristics? What are the functions?
Answer: (1) The concept of stack
· It is an ordered collection of several storage units (or registers), which sequentially store a group of elements.
· Data access can only be performed in the top unit of the stack, that is, data can only be pushed into and out of the stack through the "entrance and exit" of the top unit of the stack.
· The data in the stack adopts the "first in, last out" or "last in, first out" access working method.
(2) The role of the stack structure in the computer
· Machines with a stack structure use zero-address instructions, which is not only short in instruction length, simple in instruction structure, and simplified in machine hardware.
· Realize program call, subroutine nest call and recursive call.
· For the "interruption" technology, the stack is indispensable, saving the "breakpoint" and "site".
(3) Stack operation
Assuming that the data push direction is from high address to low address, when data is pushed into the stack, the content of SP is automatically decremented to point to a new empty stack top unit, and then the data is written into this stack top unit; when the data When the stack is popped, read out the content of the top unit pointed to by SP immediately, and then automatically increment the content of SP to point to the new top position of the stack. Right now
PUSH X； (SP)-1®SP
(X)®(SP)
POP X； ((SP))®X
(SP)+1®SP
28. What is the relationship between instruction length and machine word length? What do half-word instructions, single-word instructions, and double-word instructions represent?
Answer: There is no fixed relationship between the instruction length and the machine word length. The instruction length can be equal to the machine word length, or it can be larger or smaller than the machine word length. Usually, an instruction whose instruction length is equal to the machine word length is called a single-word instruction; an instruction whose instruction length is equal to half a machine word length is called a half-word instruction; an instruction whose instruction length is equal to two machine words is called a double-word instruction. .
29. What is the basic principle of computer program control work?
Answer: Program control principle:
(1) Programming;
(2) Send MM (via input device);
(3) When the machine is working, it takes out instructions one by one according to a certain sequence, analyzes the instructions, executes the instructions, and automatically transfers to the next instruction for execution until the task specified by the program is completed;
(4) The program control is undertaken by the controller, and the program storage is completed by the memory.
30. What is the basic function of the controller? What are the basic components?
Answer: The basic function of the controller is to be responsible for reading out instructions, identifying and interpreting them, and directing and coordinating various functional components to execute instructions. The basic structure of the controller includes: instruction unit, timing unit, micro-operation control circuit, and interrupt control logic.
31. What is the basic idea of microprogram control?
Answer: Microprogram control technology is widely used in today's computer design, and its essence is to organize the operation control logic with the thinking method of programming.
32. Explain the relationship between machine instructions and microinstructions.
Answer: There are different levels of abstraction. Machine instructions are composed of a set of binary codes. Microinstructions are control words with microaddresses. An ordered collection of a series of microinstructions constitutes a microprogram. In the microprogram control logic method, machine instructions are implemented by microprograms. The format is different. Machine instructions include opcode and operand address code fields. Microinstructions have many situations depending on the compilation method, and generally include microoperation information and lower address fields.
33. What kinds of control methods does the controller have? What are the characteristics of each?
Answer: The control mode of the controller can be divided into three types: synchronous control mode, asynchronous control mode and joint control mode.
Each operation of the synchronous control control mode is controlled by a unified timing signal, and a unified number of beat potentials and working pulses are generated in each machine cycle. This control method is simple in design and easy to implement; but for many simple instructions, there will be more idle time, resulting in a large amount of time waste, thereby affecting the execution speed of the instructions.
The various operations of the asynchronous control mode are not controlled by a unified timing signal, but are determined according to the specific conditions of the instruction or the component, as long as it takes, it takes as much time. The asynchronous control method does not waste time, thus improving the efficiency of the machine, but the control is more complicated.
The joint control method is a combination of synchronous control and asynchronous control
34. Both instructions and data are stored in the main memory, how to identify whether it is an instruction or data that is fetched from the main memory?
Answer: Instructions and data are stored in the main memory, and they all appear in the form of binary codes. The way to distinguish them is:
(1) The machine cycle in which the instruction or data is fetched is different: the instruction is fetched in the fetch cycle; the data is fetched in the analysis, fetch or execution cycle.
(2) The source of the address when fetching instructions or data is different: the instruction address comes from the program calculator; the data address comes from the address forming part.
35. What are microinstructions and microoperations? What is the relationship between microprograms and machine instructions? What is the relationship between microprogram and program?
Answer: Microinstructions are commands that control various components of a computer to complete a basic microoperation. Micro-operations refer to the most basic, non-decomposable operations in a computer. There is a one-to-one correspondence between micro-instructions and micro-operations. Micro-instructions are the control signals of micro-operations, and micro-operations are the operation process of micro-instructions. A microinstruction is a collection of several microcommands. A microprogram is a real-time interpreter of machine instructions, and each machine instruction corresponds to a microprogram.
Microprograms and programs are two different concepts. Microprograms are composed of microinstructions, which are used to describe machine instructions, and are actually real-time interpreters for machine instructions. Microprograms are compiled in advance by computer designers and stored in control memory, and are generally not provided to users; A program is made up of machine instructions, which are prepared in advance by the programmer and stored in the main memory.
36. Compare the advantages and disadvantages of horizontal microinstructions and vertical microinstructions.
Answer: (1) Horizontal microinstructions have strong parallel operation capability, high efficiency and flexibility, while vertical microinstructions are poor. (2) The horizontal microinstruction takes a short time to execute an instruction, and the vertical microinstruction takes a long time to execute. 3) The microprogram that interprets instructions by horizontal microinstructions has the characteristics of relatively long microinstruction words but short microprograms, while the vertical microinstructions are just the opposite.
(4) Horizontal micro-instructions are difficult for users to master, while vertical micro-instructions are similar to instructions and are relatively easy.
37. Compare the performance characteristics of single-bus, dual-bus and multi-bus architectures.
Answer: In the single-bus structure, the logic components connected to the bus must run at high speed, so that when some devices need to use the bus, they can quickly obtain the control of the bus; and when the bus is no longer used, they can quickly give up the control of the bus right. Otherwise, a large time delay may result because one bus is shared by multiple functional parts.
In the dual-bus structure, there are two kinds of buses: storage bus, which is used for information exchange between CPU and main memory; I/O bus, which is used for information exchange between peripherals and host.
On the basis of the dual-bus structure, in order to enable high-speed peripherals (such as disk drives) to exchange data with the main memory at high speed, direct memory access (DMA: Direct Memory Access) can be added between the high-speed peripherals and the main memory. ) high-speed I/O bus (DMA bus), thus forming a multi-bus structure
38. What are bus cycle, clock cycle, and instruction cycle? What is the general relationship between them?
Answer: The clock cycle is the minimum time unit for system work, which is determined by the main frequency of the computer; the bus cycle refers to the time required for two devices on the bus to perform an information transmission (for example, the CPU performs a read/write operation on the memory or I/O port The time required for the operation); the instruction cycle refers to the time required for the CPU to execute an instruction.
The relationship between the three is: the clock cycle is the basic unit of action; a bus cycle is usually composed of n clock cycles; and an instruction cycle may contain one or several bus cycles, or there may be no bus cycle. Depends on what the command does.
39. Explain the impact of the bus structure on the performance of the computer system.
Answer: The main impacts are as follows:
(1) Maximum storage capacity
In a single-bus system, the maximum memory size must be smaller than the possible address bus determined by the word size of the computer.
In a dual-bus system, storage capacity is not affected by the number of peripherals
(2) Command system
Dual-bus system must have a dedicated I/O command system
Single bus system, access memory and I/O use the same instruction
(3) Throughput
The greater the number of buses, the greater the throughput
40. What is the role of the interface circuit in the system structure?
Answer: The peripheral interface (or I/O interface) is the physical component between the host and the peripheral (controller), and is an essential hardware support for information exchange between the host and the peripheral.
41. What basic functions should the interface circuit have?
Answer: The basic functions that the interface circuit should have: (1) temporary storage and buffering of data; (2) saving the working status of the equipment; (3) control of information exchange mode; (6) Transformation control of data format.
42. How to address the external devices in the system and how to connect with the host?
Answer: Generally, there are two addressing methods according to the relationship with the memory address.
(1) Unified addressing: refers to the I/O registers in the peripheral interface are treated the same as the main memory unit, and they are combined with the main memory unit to program the address; or in other words, a part of the address space of the main memory is used as I/O O address space. In this way, the instruction to access the main memory can be used to access a certain register of the peripheral, so there is no need for special I/O instructions, which can simplify the design of the CPU.
(2) Separate addressing: In order to distinguish I/O operations and memory operations more clearly, I/O addresses are usually addressed separately from storage addresses. In this way, there is another I/O address that has nothing to do with the storage address in the system, and the CPU must also have I/O instructions and control logic dedicated to input and output operations.
43. What is the I/O organization method? What kinds of I/O organization methods are there? What are their respective characteristics?
Answer: I/O organization refers to the way of information exchange between the host computer and external devices. There are five ways of information exchange between the host computer and peripherals: program query, interrupt, DMA, channel, and peripheral processor.
From the point of view of system structure, the first two methods are based on CPU-centered control, and both require the CPU to execute programs for I/O data transmission, while the two methods of DMA and channel are centered on the main memory. Data can be transferred directly between main memory and peripherals. For the last way, a micro or small computer is used for input and output control. The program query and program interrupt methods are suitable for peripherals with relatively low data transfer rate, while DMA, channel and peripheral processor are used for peripheral devices with relatively high data transfer rate. The program query type control is simple, but the system efficiency is very low; the interrupt type completes the data exchange through the service program, realizing the parallelism between the host and the peripheral; the DMA type realizes the data transmission through the hardware, the speed is fast, but it can only control the same type of peripheral Design; Channel type adopts the execution channel program to realize the control and management of different types of equipment, and the parallelism is further improved; the peripheral processor mode has greater flexibility and parallelism.
44. What are the main similarities and differences between the query mode and the interrupt mode?
Answer: Both methods are CPU-centric control methods, and both require the CPU to execute programs for I/O data transmission. The program query control is simple, but the system efficiency is very low, and parallel operation cannot be realized; the interrupt type completes data exchange through the service program, and realizes the parallelism between the host and the peripheral.
45. What is an interruption? What effect does interrupt technology bring to computer systems?
Answer: Interruption refers to such a process: when the computer executes a normal program, some abnormal conditions or special requests occur in the system, the CPU suspends the program it is executing, and turns to process the event that occurred; after the CPU finishes processing, it automatically Return to the original interrupted program to continue running. Functions of interrupts: (1) Host works in parallel with external devices; (2) Real-time processing; (3) Hardware fault handling; (4) Multi-program and time-sharing operations.
46. Why does the interrupt system perform interrupt arbitration? When does interrupt arbitration take place? How to conduct arbitration?
Answer: (1) Interrupt priority has two meanings: (A) One is the issue of interrupt request and the current program priority of the CPU; (B) The other meaning is the question of who is more urgent among the various interrupt sources. (2) Method: (A) software; (B) hardware: In order to obtain higher efficiency, hardware arbitration method is generally used. The arbitration logic may have different structures depending on the arbitration scheme, and its components may be in the device interface, or inside the CPU, or both. Its function is to determine the response of the CPU and find out the highest priority requester. If it is determined to receive this request, the CPU sends an interrupt response signal INTA. (C) Combination of software and hardware. Interrupt arbitration occurs in the second step of the interrupt process, after the interrupt request and before the interrupt response.
47. What are the main functions of external devices? Can be divided into what categories? What are typical devices in each category?
Answer: The main functions of external devices include data input, output, batch storage, and information processing. Peripheral devices can be divided into five categories: input and output devices, auxiliary storage, terminal devices, process control devices, and off-line devices. Its typical equipment includes keyboards, printers, disks, intelligent terminals, digital/analog converters, and keyboard-floppy disk data stations.
48. What are the characteristics of magnetic surface memory?
Answer: Magnetic surface memory has the following notable features:
(1) High storage density, large recording capacity, and low price per bit;
(2) The recording medium can be reused;
(3) Recorded information can be stored for a long time without loss;
(4) Non-destructive readout, no need to regenerate information during readout;
(5) The access speed is low, the mechanical structure is complicated, and the requirements for the working environment are strict.
3. Analysis and Calculation Questions
1. Suppose the word length of the machine is 32 bits, the fixed-point representation, the mantissa is 31 bits, and the sign is 1 bit. Ask:
(1) What is the largest positive number when the fixed-point original code integer is represented? What is the largest negative number?
(2) What is the largest positive number when the fixed-point original code is represented by decimals? What is the largest negative number?
Answer: (1) Fixed-point original code integer representation:
Maximum positive number:
Value = (231 - 1) 10
Maximum negative number:
Value = -(231 – 1)10
(2) Fixed-point original decimal display:
Maximum positive number = (1 – 2-31) 10
Maximum negative number = -(1 - 2-31) 10
2. If the existing 1024×1 memory chip is used to form a memory with a capacity of 16K×8. Try to find:
(1) How many chips are required to implement this memory?
(2) If these chips are divided into several boards, and the capacity of each board is 4K×8, what is the total number of address lines required by the memory? How many of them are used for board selection? How many people are used for film selection? How many bits are used as on-chip address?
Answer: (1) 128 chips of 1024×1 are required.
(2) The total number of address lines required by the memory is 14 bits, of which 2 bits are used for board selection, 2 bits are used for chip selection, and 10 bits are used as on-chip addresses.
3. Assume that the memory capacity is 32 bits, the word length is 64 bits, and the number of modules is m = 8, which are organized in a sequential way and an interleaved way respectively. If the storage period T = 200ns, the data bus width is 64 bits, and the bus transfer period is 50ns, what is the bandwidth of the sequential memory and the interleaved memory?
Answer: The total amount of information of m=8 words continuously read out by the sequential memory and the interleaved memory is:
q = 64 bits x 8 = 512 bits
The time required for sequential memory and interleaved memory to continuously read 8 words are:
t2 = mT = 8 × 200ns =1600ns =16 × 10 -7 （S）
t1 = T + （m–1）t =200ns + 7×50ns = 550ns = 5.5 × 10-7 （S）
Sequential memory bandwidth W2 = q/t2 = 512 / (16 × 10-7) = 32 × 107 (bits/S)
Interleaved memory bandwidth W1 = q/t1 = 512/(5.5×10-7) = 73×107 (bits/S)
4. There are 16 address buses of the CPU (A15~A0, A0 is low), 16 bidirectional data buses (D15~D0), and the signals related to the main memory in the control bus are !MREQ (allowing memory access, active low ), R/!W (high level read command, low level write command). The main memory address space is allocated as follows: 0~8191 is the system program area, which is composed of EPROM chips. From 8192 onwards, a total of 32K address space is the user program area, and the last (maximum address) 4K address space is the system program work area. As shown in Figure 1. The above addresses are in decimal system and are addressed by word. The following chips are available.
EPROM: 8K×16 bits (the control terminal only has !CS), 16 bits×8 bits
SRAM: 16K×1 bit, 2K×8 bit, 4K×16 bit, 8K×16 bit
Please choose a chip from the above-mentioned chips to design the main memory of the computer, and draw the logic block diagram of the main memory.
Figure 1 Address Allocation
Answer: The main memory address distribution and chip connection diagram are shown in Figure 2. According to the given conditions, select one EPROM 8K×16-bit chip, four SRAM 8K×16-bit chips, one 4K×16-bit chip, one 3:8 decoder, NAND gate and inverter.
A12-A0 for on-chip decoding
A15-A13 for off-chip decoding (8 groups)
Figure 2 Main memory address distribution and chip connection diagram
5. The word length of a computer instruction is 16 bits, and the address code is 6 bits. The instruction has three formats: no address, first address, and second address. How many?
Solution: Let there be X instructions for 1 address
（（24-N）*26-X）*26=M
Get: X=(24-N)*26-M*2-6
6. Assume that a computer instruction is 20 bits in length and has three types of instruction formats: double operand, single operand and no operand, and the address of each operand is specified to be represented by 6 bits. Question: If the opcode field is fixed at 8 bits, m double-operand instructions and n no-operand instructions have been designed. In this case, how many single-operand instructions can this computer design at most?
Answer: Since all instructions are set to use 8-bit fixed OP fields, the maximum number of instructions for this computer is 28=256
strip. Therefore, at most (256-mn) single-operand instructions can be designed.
7. There are 4-stage pipelines to complete the 4-step operations of fetching instructions, decoding instructions and fetching numbers, computing, and sending results. It is assumed that the time to complete each step is 100ns, 80ns, and 50ns.
(1) What should be the operating cycle of the pipeline?
(2) If data correlation occurs between two adjacent instructions, and no measures are taken on the hardware, how long should the second instruction be delayed?
(3) If improvements are made in hardware design, how much time should be delayed at least?
untie:
(1) The operating clock cycle t of the pipeline is considered as the longest time among the four-step operations, so t=100ns.
(2) Data-related conflicts occur between two instructions:
ADD R1，R2，R3； R2+R3->R1
SUB R4，R1，R5； R1-R5->R4
The execution of the two instructions in the pipeline is shown in Table 6-4:
Table 6-4 Execution of instructions on the pipeline
| clock instruction |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
| ADD |
I |
D |
E |
W |
|||
| SUB |
I |
D |
E |
W |
The ADD instruction writes the result to the register file (R1) at clock 4, but the SUB instruction reads the register file (R1) at clock 3. Originally, the ADD instruction should be written into R1 first, and then read R1 after the SUB instruction. As a result, the SUB instruction reads R1 first, and then writes R1 after the ADD instruction. Therefore, data correlation between the two instructions occurs. If no measures are taken on the hardware, the second instruction SUB should be delayed by at least 2 operating clock cycles (2×100ns).
(3) If the hardware is improved (bypass technology), one operating clock cycle (100ns) can be delayed.
8. The instruction pipeline has five process segments: right fetch (IF), decoding (ID), execution (EX), memory access (MEM), and write back to the register file (WB). A total of 20 instructions are continuously input into this pipeline.
(1) Draw the time-space diagram of pipeline processing, assuming that the clock cycle is 100ns.
(2) Find the actual throughput rate of the pipeline (the number of instructions executed per unit time).
Solution: (1)
（2）
9. One access cycle of a certain system bus is the fastest 3 bus clock cycles, and 32-bit data can be accessed in one bus cycle. If the clock frequency of the bus is 8.33MHz, what is the bandwidth of the bus in MB/s?
Solution: Bus bandwidth = data width × maximum frequency of bus cycle
=（32/8）Byte×（8.33/3）M/s
= 11.1 MB/s
10. A disk pack has 6 disks, each disk can have 2 recording surfaces, the inner diameter of the storage area is 22cm, the outer diameter is 33cm, the track density is 40 tracks/cm, the bit density is 400b/cm, and the rotation speed is 2400 r/min. Just ask:
(1) How many storage planes are available?
(2) How many cylindrical surfaces are there?
(3) What is the total storage capacity of the entire disk group?
(4) What is the data transfer rate?
(5) If the length of a certain file exceeds the capacity of one disk, should it be recorded on the same storage plane or on the same cylindrical plane? Why?
(6) If the fixed-length information block record format is adopted, what is the minimum unit of direct addressing? How to represent the disk address in the addressing command?
Answer: (1) 6×2=12 (planes), there are 12 storage planes available.
(2) 40×(33－22)/2=220 (tracks), there are 220 cylindrical surfaces in total.
(3) 12×22π×400×220=73×106 (bits).
(4) Data transmission rate=(22π×400)/(60/2400)=1.1×106 (b/s)=0.138×106 (B/s).
(5) Record on the same cylindrical surface. Because the access speed is arranged in this way.
(6) If the fixed-length information block recording format is adopted, the smallest unit of direct addressing is a sector. Disk address: drive letter, cylinder number, disk number, sector number.
11. The rotational speed of a certain disk storage is 3000r/min, there are 4 recording surfaces, 5 tracks/mm, and the information recorded in each track is 12288B, the minimum track diameter is 230mm, and there are 275 tracks in total. Question:
(1) What is the storage capacity of the disk storage?
(2) What is the maximum bit density, and what is the minimum bit density?
(3) What is the disk data transfer rate?
(4) What is the average waiting time?
Give a disk address format scheme.
Answer: (1) The information capacity of each record = 12288 bytes, the information capacity of each recording surface = 275×12288 bytes, and there are 4 recording surfaces in total, so the total capacity of the disk storage is
4 x 275 x 12288 bytes = 13516800 bytes
(2) The highest bit density D1 is calculated according to the minimum track radius R1 (R1 = 115mm):
D1 = 12288 bytes/2πR1= 17 bytes/mm
The lowest bit density D2 is calculated according to the maximum track radius R2
R2 = R1 + (275/5) = 115 + 55 = 170mm
D2 = 12288 bytes/2πR2 = 11.5 bytes/mm
(3) Disk data transfer rate
r = 3000/60 = 50 cycles/second
N = 12288 bytes (information capacity per channel)
C = r×N = 50×12288 = 614400 bytes/sec
(4) Average waiting time = 1/2r = 1/2 x 50 = 1/100 second = 10 milliseconds
(5) It is assumed that there is only one local disk storage. There are 4 recording surfaces, and each recording surface has 275 tracks. Assuming that each sector records 1024 bytes, 12288 bytes/1024 bytes = 12 sectors are required. From this, the address format shown in Figure 9-29 can be obtained:
14 6 5 4 3 0
| Cylinder (track) number |
Disk (head) number |
sector number |
Figure 9-29 Address format
12. A disk group with 6 disks, the rotation speed is 2400r/min (rotation speed per minute), the outer diameter of the effective recording area on the disk surface is 30cm, the inner diameter is 20cm, and the recording density is 640b/m (bits per millimeter) number), the track pitch is 0.2cm, the platter has 2 protection surfaces and 1 servo surface. Try to calculate:
(1) The storage capacity of the disk group.
(2) Data transfer rate.
Solution: (note that uniform units are required)
（1）（2*6-3）*（30-20）/2/0.2*(2*20/2*PI*640)
（2） (2*20/2*PI*640)*2400/60
13. There are two floating-point numbers x=2 Ex×Sx, y=2 Ey×Sy, Ex=(-10)2, Sx=(+0.1001)2, Ey=(+10)2, Sy=(+ 0.1011) 2. If the mantissa is 4 digits, the number symbol is 1 digit, the exponent code is 2 digits, and the exponent symbol is 1 digit, find x+y and write down the operation steps and results.
untie:
because
, the calculation of X+Y needs to go through the steps of order, mantissa summation and normalization.
(1) Matching order:
△J=Ex－Ey=(-10)2－(+10)2=(-100)2 So Ex<Ey, then Sx is shifted to the right by 4 bits, Ex+(100)2=(10)2=Ey. Sx=0.00001001 after Sx is shifted to the right by four bits, SX=0001 after rounding, after order adjustment and rounding,
(2) Mantissa sum: Sx+Sy
0.0001（Sx）
+ 0.1011（Sy）
Sx+Sy=0.1100
The result is a normalized number.
14. There are two decimal numbers, x = -0.875 × 21, y = 0.625 × 22:
(1) Convert the mantissas of x and y to two's complement form.
(2) Set the exponent code to 2 bits, the exponent to 1 bit, the number sign to 1 bit, and the mantissa to 3 bits, and obtain the binary floating-point normalization result of z = x – y through the complement code operation rules.
untie:
(1) Let S1 be the mantissa of x and S2 be the mantissa of y, then
S1 = （-0.875）10 = （-0.111）2
[S1] complement = 1.001
S2 = （0.625）10 = （+0.101）2
[S2] complement = 0.101
(2) Find the binary floating-point normalization result of z = x – y.
(A) Matching order:
Let the order code of x be jx, the order code of y be jy, jx = (+01)2, jy = (+10)2,
jx – jy = (01) 2 – (10) 2 = (-01) 2, the mantissa S1 of the small order is shifted to the right by one bit,
S1 = (-0.0111) 2, jx order code plus 1, then jx = (10) 2 = jy, after rounding,
S1 = (-0,100) 2, the alignment is complete.
(B) Mantissa subtraction
[S1] complement = 11.100
+[-S2] complement = 11.011
[S1-S2] Complement = 10.111 The absolute value of the mantissa sum is greater than 1
The mantissa is shifted one bit to the right, the least significant bit is discarded, and the exponent code is added by 1 (right rule), then [S1-S2] complement = 11.011 (normalized number), jx = jy = 11
(C) Normalized result 011.1011